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SSM2518CPZ-R7 Scheda tecnica(PDF) 46 Page - Analog Devices |
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SSM2518CPZ-R7 Scheda tecnica(HTML) 46 Page - Analog Devices |
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46 / 48 page ![]() SSM2518 Data Sheet Rev. A | Page 46 of 48 DRC CONTROL 9 REGISTER Address: 0x12, Reset: 0x07, Name: DRC_Control_9 Table 31. Bit Descriptions for DRC_Control_9 Bits Bit Name Settings Description Reset Access [7:4] RESERVED Reserved. 0x0 RW [3:0] RMS_TAV DRC RMS Detector Averaging Time. This is the averaging time for the rms level that is compared to the DRC thresholds. 0x7 RW 0000 0 ms 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms 1000 192 ms 1001 384 ms 1010 768 ms 1011 1.536 sec 1100 3.072 sec 1101 6.144 sec 1110 12.288 sec 1111 24.576 sec |
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