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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SSM2518CPZ-R7 Scheda tecnica(PDF) 7 Page - Analog Devices |
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SSM2518CPZ-R7 Scheda tecnica(HTML) 7 Page - Analog Devices |
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7 / 48 page  Data Sheet SSM2518 Rev. A | Page 7 of 48 DIGITAL TIMING All timing specifications are given for the default setting (I2S mode) of the serial input port. Table 5. Limit Parameter Min Max Unit Description MASTER CLOCK tMP 74 136 ns MCLK period, 256 × fS mode (MCS = b0010) tMP 148 271 ns MCLK period, 128 × fS mode (MCS = b0001) SERIAL PORT tBIL 40 ns BCLK low pulse width tBIH 40 ns BCLK high pulse width tLIS 10 ns Setup time from LRCLK or SDATA edge to BCLK rising edge tLIH 10 ns Hold time from BCLK rising edge to LRCLK or SDATA edge tSIS 10 ns SDATA setup time to BCLK rising tSIH 10 ns SDATA hold time from BCLK rising I2C PORT fSCL 400 kHz SCL frequency tSCLH 0.6 μs SCL high tSCLL 1.3 μs SCL low tSCS 0.6 μs Setup time; relevant for repeated start condition tSCH 0.6 μs Hold time; after this period, the first clock is generated tDS 100 ns Data setup time tSCR 300 ns SCL rise time tSCF 300 ns SCL fall time tSDR 300 ns SDA rise time tSDF 300 ns SDA fall time tBFT 0.6 μs Bus-free time (time between stop and start) Digital Timing Diagrams tSIS tSIH tSIS tSIH tLIH tBP tBIH BCLK LRCLK SDATA LEFT-JUSTIFIED MODE SDATA I2C-JUSTIFIED MODE SDATA RIGHT-JUSTIFIED MODE tBIL tLIS tSIS tSIH tSIS tSIH MSB MSB MSB LSB MSB – 1 Figure 2. Serial Input Port Timing tSCH tSCS tBFT tSCF tDS tSCLL tSCR tSCLH tSCH STOP CONDITION START CONDITION SDA SCL Figure 3. I2C Port Timing |
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