MPC8378E datasheet(43/128 Pages) FREESCALE

43 / 128 page

MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This table describes the general timing parameters of the local bus interface of the device when in PLL

bypass mode.

This figure provides the AC test load for the local bus.

Figure 23. Local Bus AC Test Load

Table 45. Local Bus General Timing Parameters—PLL Bypass Mode

Parameter

Symbol1

Min

Max

Unit

Note

Local bus cycle time

tLBK

—

Input setup to local bus clock

tLBIVKH

7.0

—

3, 4

Input hold from local bus clock

tLBIXKH

1.0

—

3, 4

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT1

1.5

—

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT2

3.0

—

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT3

2.5

—

Local bus clock to LALE rise

tLBKHLR

—4.5

—

Local bus clock to output valid

tLBKHOV

—3.0

Local bus clock to output high impedance for LAD/LDP

tLBKHOZ

—

4.0

3, 8

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes

high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go

high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from LBVDD/2 of the rising/falling edge of LCLK0 to 0.4 × LBVDD of the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load

on LAD output pins.

7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

MPC8378E Scheda tecnica(PDF) 43 Page - Freescale Semiconductor, Inc

MPC8378E Scheda tecnica(HTML) 43 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL