AD6623SSLASHPCB datasheet(30/40 Pages) AD

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AD6623

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internal registers, External Address [0] must be written last to

insure all data is transferred. Reads are the opposite in that

External Address [0] must be the first data register read (after setting

the appropriate internal address) to initiate an internal access.

External Address [5:4] reads and writes are transferred immediately

to internal control registers. External Address [4] is the sleep register.

The sleep bits can be set collectively by the address. The sleep bits

can be cleared by operation of start syncs (described below).

External Address [5] is the sync register. These bits are write only.

There are three types of syncs: start, hop, and beam. Each of these

can be sent to any or all of the four channels. For example, a write of

X0010100

would issue a start sync to channel C only. A write of

X1101111

would issue a beam sync and a hop sync to all channels.

The internal address bus is 12 bits wide and the internal data bus

is 32 bits wide. External address 7 is the UAR (Upper Address

UAR[3:0]. UAR[7:6] define the auto-increment feature. If Bit 6

is high, the internal address is incremented after an internal read.

If Bit 7 is high, the internal address is incremented after an internal

write. If both bits are high, the internal address in incremented

after either a write or a read. This feature is designed for sequential

access to internal locations. External address 6 is the LAR (Lower

Address Register) and stores the lower 8 bits of the internal

address. External addresses 3 through 0 store the 32 bits of the

internal data. All internal accesses are two clock cycles long.

Writing to an internal location with a data width of 16 bits is

achieved by first writing the upper four bits of the address to bits

3 through 0 of the UAR (bits 7 and 6 of the UAR are written to

determine whether or not the auto increment feature is enabled).

The LAR is then written with the lower eight bits of the internal

address (it doesn’t matter if the LAR is written before the UAR as

long as both are written before the internal access). Since the data

width of the internal address is 16 bits, only data register 1 and data

the write to data register 0 triggers the internal access. Data register

0 must always be the last register written to initiate the internal write.

Reading from the MicroPort is accomplished in a similar manner.

The internal address is first written. A read from data register 0

activates the internal read, thus register 0 must always be read first

to initiate an internal read. This provides the 8 LSBs of the internal

read through the MicroPort (D[7:0]). Additional bytes are then

read by changing the external address (A[2:0]) and performing

additional reads. If data register 3 (or any other) is read before

data register 0, incorrect data will be read. Data register 0 must

be read first in order to transfer data from the core memory to the

external memory locations. Once the data register is read, the remaining

locations may be examined in any order.

Access to the external registers of Table XX is accomplished

in one of two modes using the

CS, DS(RD), RW(WR), and

DTACK(RDY) inputs. The access modes are Intel Nonmulti-

plexed mode and Motorola Nonmultiplexed mode. These modes

are controlled by the MODE input (MODE = 0 for INM,

MODE = 1 for MNM).

Intel Nonmultiplexed Mode (INM)

MODE must be tied low to operate the AD6623 MicroPort in

INM mode. The access type is controlled by the user with the

chip select (

CS), read (RD), and write (WR) inputs. The ready

(RDY) signal is produced by the MicroPort to communicate to

the user the MicroPort is ready for an access. RDY goes low at

the start of the access and is released when the internal cycle is

complete. See the timing diagrams for both the read and write

modes in the Specifications.

Motorola Nonmultiplexed Mode (MNM)

MODE must be tied high to operate the AD6623 MicroPort in

MNM mode. The access type is controlled by the user with the

chip select (

CS), data strobe (DS), and read/write (RW) inputs.

The data acknowledge (

DTACK) signal is produced by the

MicroPort to acknowledge the completion of an access to the user.

DTACK goes low when an internal access is complete and then

will return high after

DS is deasserted. See the timing diagrams

for both the read and write modes in the Specifications.

The

DTACK(RDY) pin is configured as an open drain so that

multiple devices may be tied together at the microprocessor/

microcontroller without contention.

The MicroPort of the AD6623 allows for multiple accesses while

CS is held low (CS can be tied permanently low if the MicroPort

is not shared with additional devices). The user can access multiple

locations by pulsing the RW(

WR) or DS(RD) lines and changing

the contents of the external three bit address bus (A[2:0]).

External Address 7 Upper Address Register (UAR)

Sets the four most significant bits of the internal address, effectively

selecting channels 1, 2, 3, or 4 (D2:D0). The autoincrement of

read and write are also set (D7:D6).

External Address 6 Lower Address Register (LAR)

Sets the internal address 8 LSBs (D7:D0).

External Address 5 Sync

This register is write only. Bits in this address control the synchro-

nization of the AD6623 channels. If the user intends to bring up

channels with no synchronization requirements then all bits of this

with the AD6623. The first is Soft Sync. Soft Sync is software

synchronization enabled through the MicroPort. The second

synchronization method is Pin Sync. Pin Sync is enabled by a signal

Table XXI. External Registers

External Data

External Address

7:UAR

Wrinc

Rdinc

––

IAII

IAIO

IA9

IA8

6:LAR

IA7

IA6

IA5

IA4

IA3

IA2

IA1

IA0

5:Sync

–

Beam

Hop

Start

Sync D

Sync C

Sync B

Sync A

4:Sleep

Prog D

Prog C

Prog B

Prog A

Sleep D

Sleep C

Sleep B

Sleep A

3:Byte3

ID31

ID30

ID29

ID28

ID27

ID26

ID25

ID24

2:Byte2

ID23

ID22

ID21

ID20

ID19

ID18

ID17

ID16

1:Byte1

ID15

ID14

ID13

ID12

ID11

ID10

ID9

ID8

0:Byte0

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

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