AD6623SSLASHPCB datasheet(16/40 Pages) AD

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PROGRAMMABLE RAM COEFFICIENT FILTER (RCF)

Each channel has a fully independent RAM Coefficient Filter (RCF).

The RCF accepts data from the Serial Port, processes it, and passes

the resultant I and Q data to the CIC filter. A variety of processing

options may be selected individually or in combination, including

PSK and MSK modulation, FIR filtering, all-pass phase equalization,

and scaling with arbitrary ramping. See Table III.

Table III. Data Format Processing Options

Processing Block

Input Data

Output Data

Interpolating FIR Filter

I and Q

PSK Modulator

2 or 3 bits

per symbol

Unfiltered I

and Q:

/4-QPSK,

8-PSK, or

3 /8-8-PSK

MSK Modulator

1 bit per symbol

Filtered MSK

or GSM I and Q

QPSK

2 bits per symbol

Filtered QPSK

I and Q

All-pass Phase Equalizer

I and Q

Scale and Ramp

I and Q

OVERVIEW OF THE RCF BLOCKS

The Serial Port passes data to the RCF with the appropriate

format and bit precision for each RCF configuration, see Figure 17.

The data may be modulated vectors or unmodulated bits. I and

Q vectors are sent directly to the Interpolating Fir Filter. Unmodu-

lated bits may be sent to the PSK Modulator, the Interpolating

MSK Modulator, or the Interpolating QPSK Modulator. The PSK

Modulator produces unfiltered I and Q vectors at the symbol

rate which are then passed through the Interpolating FIR Filter.

The Interpolating MSK Modulator and the Interpolating QPSK

Modulator produce oversampled, pulse-shaped vectors directly

without employing the Interpolating FIR Filter. When possible,

the MSK and QPSK modulators are recommended for increased

throughput and decreased power consumption compared to

Interpolating FIR Filter. In addition, the Interpolating MSK

Modulator can realize filters with nonlinear inter-symbol inter-

ference, achieving excellent accuracy for GMSK applications.

After interpolation, an optional Allpass Phase Equalizer (APE)

can be inserted into the signal path. The APE can realize any real,

stable, two-pole, two-zero all-pass filter at the RCF’s interpolated

rate. This is especially useful to precompensate for nonlinear

phase responses of receive filters in terminals, as specified by IS-95.

When active, the APE utilizes shared hardware with the interpo-

lating modulators and filter, which may reduce the allowed RCF

throughput, inter-symbol interference, or both. See Figure 18.

tDSDFO0A

tHSDI0

SCLK

SDFO

SDI

DATAn

CLK

tSSDI0

CLKn

tSSDI0

Figure 16. Serial Port Switching Characteristics

As an example of the Serial Port operation, consider a CLK fre-

quency of 62.208 MHz and a channel interpolation of 2560. In

that case, the input sample rate is 24.3 kSPS (62.208 MHz/2560),

which is also the SDFO rate. Substituting, fSCLK

≥ 32

fSDFO

into the equation and solving for SCLKdivider, we find the mini-

mum value for SCLKdivider according to the equation below.

SCLKdivider

CLK

SFDO

≤

(3)

Evaluating this equation for our example, SCLKdivider must be

less than or equal to 79. Since the SCLKdivider channel register

is a 5-bit unsigned number it can only range from 0 to 31.

Any value in that range will be valid for this example, but if it is

important that the SDFO period is constant, then there is another

restriction. For regular frames, the ratio fSCLK/fSDFO must be equal

to an integer of 32 or larger. For this example, constant SDFO

periods can only be achieved with an SCLK divider of 31 or less.

See Table II for usable SCLK divider values and the corresponding

SCLK and fSCLK/fSDFO ratio for the example of L = 2560.

In conclusion, SDFO rate is determined by the AD6623 CLK

rate and the interpolation rate of the channel. The SDFO rate is

equal to the channel input rate. The channel interpolation is

equal to RCF interpolation times CIC5 interpolation, times

CIC2 interpolation:

RCF

CIC

CRIC

=×









(4)

The SCLK divide ratio is determined by SCLKdivider as shown

in the previous equation. The SCLK must be fast enough to

input 32 bits of data prior to the next SDFO. Extra SCLKs are

ignored by the serial port.

Table II. Example of Usable SCLK Divider

Values and fSCLK/fSDPO Ratios for L = 2560

SCLKdivisor

fSCLK/fSDFO

2560

1280

640

512

320

256

160

128

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