AD6623SSLASHPCB datasheet(15/40 Pages) AD

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AD6623

–15–

SERIAL DATA PORT

The AD6623 has four independent Serial Ports (A, B, C, and D),

and each accepts data to its own channel (A, B, C, or D) of the

device. Each Serial Port has four pins: SCLK (Serial CLocK), SDFO

(Serial Data Frame Out), SDFI (Serial Data Frame In), and SDIN

(Serial Data INput). SDFI and SDIN are inputs, SDFO is an output,

and SCLK is either input or output depending on the state of SCS

(Serial Clock Slave: 0xn16, Bit 4). Each channel can be operated

either as a Master or Slave channel depending upon SCS. The Serial

Port can be self-framing or accept external framing from the SFDI

pin or from the previous adjacent channel (0xn16, Bits 7 and 6).

Serial Master Mode (SCS = 0)

In master mode, SCLK is created by a programmable internal

counter that divides CLK. When the channel is “sleeping,” SCLK

is held low. SCLK becomes active on the first rising edge of CLK

after Channel sleep is removed (D0 through D3 of external

address 4). Once active, the SCLK frequency is determined by

the CLK frequency and the SCLK divider, according to the

equations below.

AD6623 mode:

SCLKdivider

SCLK

CLK

+ 1

(1)

AD6622 mode:

SCLKdivider

SCLK

CLK

×+

()

(2)

The SCLK divider is a 5-bit unsigned value located at Internal

Channel Address 0xn0D (Bits 4–0), where “n” is 1, 2, 3, or 4 for

the chosen channel A, B, C, or D, respectively. The user must

select the SCLK divider to insure that SCLK is fast enough to

accept full input sample words at the input sample rate. See the

design example at the end of this section. The maximum SCLK

frequency is equal to the CLK when operating in AD6623 mode

serial clock master. When operating in AD6622 compatible mode,

the maximum SCLK frequency is one-half the CLK. The minimum

SCLK frequency is 1/32 of the CLK frequency in AD6623 mode

or 1/64 of the CLK frequency when in AD6622 mode. SDFO

changes on the positive edge of SCLK when in master mode. SDIN

is captured on positive edge when SCLK is in master mode.

Serial Slave Mode (SCS = 1)

Any of the AD6623 serial ports may be operated in the serial slave

mode. In this mode, the selected AD6623 channel requires that

an external device such as a DSP to supply the SCLK. This is

done to synchronize the serial port to meet an external timing

requirement. SDIN is captured on negative edge of SCLK when

in slave mode.

Self-Framing Mode

In this mode Bit 7 of register 0xn16 is set low. The serial data

frame output, SDFO, generates a self-framing data request and

is pulsed high for one SCLK cycle at the input sample rate. In

this mode, the SDFI pin is not used, and the SDFO signal would

be programmed to be a serial data frame request (0xn16, Bit 5 = 0).

SDFO is used to provide a sync signal to the host. The input

sample rate is determined by the CLK divided by channel interpo-

lation factor. If the SCLK rate is not an integer multiple of the

input sample rate, then the SDFO will continually adjust the

period by one SCLK cycle to keep the average SDFO rate equal

to the input sample rate. When the channel is in sleep mode, SDFO

is held low. The first SDFO is delayed by the channel reset latency

after the Channel Reset is removed. The channel reset latency

varies dependent on channel configuration.

External Framing Mode

In this mode Bit 7 of register 0xn16 is set high. The external

framing can come from either the SDFI pin (0xn16, Bit 6 = 0)

or the previous adjacent channel (0xn16, Bit 6 = 1). In the case

of external framing from a previous channel, it uses the internal

frame end signal for serial data frame syncing. When in master

mode, SDFO and SDFI transition on the positive edge of SCLK,

and SDIN is captured on the positive edge of SCLK. When in

slave mode, SDFO and SDFI transition on the negative edge of

SCLK, and SDIN is captured on the negative edge of SCLK.

Serial Port Cascade Configuration

In this case the SDFO signal from the last channel of the first

chip would be programmed to be a serial data frame end (SFE:

0xn16, Bit 5 = 1). This SDFO signal would then be fed as an

input for the second cascaded chip’s SDFI pin input. The second

chip would be programmed to accept external framing from the

SDFI pin (0xn16, Bit 7 = 1, Bit 6 = 0).

Serial Data Format

The format of data applied to the serial port is determined by

the RCF mode selected in Control Register 0xn0C. Below is a

table showing the RCF modes and input data format that it sets.

Table I. Serial Data Format

0xn0C

Serial Data

RCF

Bit 6

Bit 5

Bit 4

Word Length

Mode

0032

FIR

/4-DQPSK

GMSK

MSK

24 (Bit 9 is high)

16 (Bit 9 is low)

FIR,

compact

8-PSK

3 /8-8-PSK

QPSK

The serial data input, SDIN, accepts 32-bit words as channel input

data. The 32-bit word is interpreted as two 16-bit two’s comple-

ment quadrature words, I followed by Q, MSB first. This results in

linear I and Q data being provided to the RCF. The first bit is

shifted into the serial port starting on the next rising edge of SCLK

after the SDFO pulse. Figure 16 shows a timing diagram for SCLK

master (SCS = 0) and SDFO set for frame request (SFE = 0).

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