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MC68331TS Scheda tecnica(PDF) 35 Page - Freescale Semiconductor, Inc |
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MC68331TS Scheda tecnica(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 84 page ![]() MC68331TS/D 35 3.6 General-Purpose Input/Output SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de- scribe registers that control the ports. A write to the port E data register is stored in the internal data latch and, if any port E pin is configured as an output, the value stored for that bit is driven on the pin. A read of the port E data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. The port E data register is a single register that can be accessed in two locations. When accessed at $YFFA11, the register is referred to as PORTE0; when accessed at $YFFA13, the register is referred to as PORTE1. The register can be read or written at any time. It is unaffected by reset. The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. This register can be read or written at any time. The bits in this register control the function of each port E pin. Any bit set to one configures the corre- sponding pin as a bus control signal, with the function shown in the following table. Any bit cleared to zero defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE. Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero during reset, this register is set to $00, configuring all port E pins as I/O pins. Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be a bus control signal. PORTE0, PORTE1 —Port E Data Register $YFFA11, $YFFA13 15 8 7 6 5 4 3 2 1 0 NOT USED PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 RESET: U U U U U U U U DDRE — Port E Data Direction Register $YFFA15 15 8 7 6 5 4 3 2 1 0 NOT USED DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 RESET: 0 0 0 0 0 0 0 0 PEPAR — Port E Pin Assignment Register $YFFA17 15 8 7 6 5 4 3 2 1 0 NOT USED PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 RESET: DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 Table 16 Port E Pin Assignments PEPAR Bit Port E Signal Bus Control Signal PEPA7 PE7 SIZ1 PEPA6 PE6 SIZ0 PEPA5 PE5 AS PEPA4 PE4 DS PEPA3 PE3 RMC PEPA2 PE2 AVEC PEPA1 PE1 DSACK1 PEPA0 PE0 DSACK0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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