MC68331TS datasheet(52/84 Pages) FREESCALE

52 / 84 page

MC68331TS/D

Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR

5.2 Pin Function

The following table is a summary of the functions of the QSM pins when they are not configured for gen-

eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in-

put or output.

Table 22 QSM Address Map

Access

Address

8 7

$YFFC00

QSM MODULE CONFIGURATION (QSMCR)

$YFFC02

QSM TEST (QTEST)

$YFFC04

QSM INTERRUPT LEVEL (QILR)

QSM INTERRUPT VECTOR (QIVR)

S/U

$YFFC06

NOT USED

S/U

$YFFC08

SCI CONTROL 0 (SCCR0)

S/U

$YFFC0A

SCI CONTROL 1 (SCCR1)

S/U

$YFFC0C

SCI STATUS (SCSR)

S/U

$YFFC0E

SCI DATA (SCDR)

S/U

$YFFC10

NOT USED

S/U

$YFFC12

NOT USED

S/U

$YFFC14

NOT USED

PQS DATA (PORTQS)

S/U

$YFFC16

PQS PIN ASSIGNMENT (PQSPAR)

PQS DATA DIRECTION (DDRQS)

S/U

$YFFC18

SPI CONTROL 0 (SPCR0)

S/U

$YFFC1A

SPI CONTROL 1 (SPCR1)

S/U

$YFFC1C

SPI CONTROL 2 (SPCR2)

S/U

$YFFC1E

SPI CONTROL 3 (SPCR3)

SPI STATUS (SPSR)

S/U

$YFFC20–

$YFFCFF

NOT USED

S/U

$YFFD00–

$YFFD1F

RECEIVE RAM (RR[0:F])

S/U

$YFFD20–

$YFFD3F

TRANSMIT RAM (TR[0:F])

S/U

$YFFD40–

$YFFD4F

COMMAND RAM (CR[0:F])

Mode

Pin Function

MISO

Master

Serial Data Input to QSPI

QSPI Pins

Slave

Serial Data Output from QSPI

MOSI

Master

Serial Data Output from QSPI

Slave

Serial Data Input to QSPI

SCK

Master

Clock Output from QSPI

Slave

Clock Input to QSPI

PCS0/SSMaster

Input: Assertion Causes Mode Fault

Output: Selects Peripherals

Slave

Input: Selects the QSPI

PCS[3:1]

Master

Output: Selects Peripherals

Slave

None

SCI Pins

TXD

Transmit

Serial Data Output from SCI

RXD

Receive

Serial Data Input to SCI

Freescale Semiconductor, Inc.

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