ADS1606IPAPR datasheet(20/38 Pages) TI

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ADS1605

ADS1606

SBAS274H − MARCH 2003 − REVISED MAY 2007

www.ti.com

CLOCK INPUT (CLK)

The ADS1605/6 requires an external clock signal to be

applied to the CLK input pin. The sampling of the modu-

lator is controlled by this clock signal. As with any high-

speed data converter, a high quality clock is essential

for optimum performance. Crystal clock oscillators are

the recommended CLK source; other sources such as

frequency synthesizers are usually not adequate. Make

sure to avoid excess ringing on the CLK input; keeping

the trace as short as possible will help.

Measuring high frequency, large amplitude signals re-

quires tight control of clock jitter. The uncertainty during

sampling of the input from clock jitter limits the maxi-

mum achievable SNR. This effect becomes more pro-

nounced with higher frequency and larger magnitude in-

puts.

Fortunately,

the

ADS1605/6

oversampling

topology reduces clock jitter sensitivity over that of Ny-

quist rate converters like pipeline and successive

approximation converters by a factor of 8.

In order to not limit the ADS1605/6 SNR performance,

keep the jitter on the clock source below the values

shown in Table 1. When measuring lower frequency

and lower amplitude inputs, more CLK jitter can be tol-

erated. In determining the allowable clock source jitter,

select the worst-case input (highest frequency, largest

amplitude) that will be seen in the application.

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

INPUT SIGNAL

MAXIMUM

ALLOWABLE

MAXIMUM

FREQUENCY

MAXIMUM

AMPLITUDE

ALLOWABLE

CLOCK SOURCE

JITTER

2MHz

−2dB

1.9ps

2MHz

−20dB

14ps

1MHz

−2dB

3.8ps

1MHz

−20dB

28ps

500kHz

−2dB

7.6ps

500kHz

−20dB

57ps

100kHz

−2dB

38ps

100kHz

−20dB

285ps

DATA FORMAT

The 16-bit output data are in binary two’s complement

format as shown in Table 2. When the input is positive

out-of-range, exceeding the positive full-scale value of

1.467VREF, the output clips to all 7FFFh and the OTR

output goes high.

Likewise, when the input is negative out-of-range by go-

ing below the negative full-scale value of –1.467VREF,

the output clips to 8000h and the OTR output goes high.

The OTR remains high while the input signal is out-of-

range.

Table 2. Output Code Versus Input Signal

INPUT SIGNAL

(INP – INN)

IDEAL OUTPUT

CODE(1)

OTR

≥+1.467VREF (> 0dB)

7FFFH

1.467VREF (0dB)

7FFFH

+1.467V

REF

215

* 1

0001H

0000H

−1.467V

REF

215

* 1

FFFFH

−1.467V

REF

215

* 1

8000H

v −1.467V

REF

215

* 1

8000H

(1) Excludes effects of noise, INL, offset and gain errors.

OUT-OF-RANGE INDICATION (OTR)

If the output code on DOUT[15:0] exceeds the positive

or negative full-scale, the out-of-range digital output

OTR will go high on the falling edge of DRDY. When the

output code returns within the full-scale range, OTR re-

turns low on the falling edge of DRDY.

DATA RETRIEVAL

Data retrieval is controlled through a simple parallel in-

terface. The falling edge of the DRDY output indicates

new data are available. To activate the output bus, both

CS and RD must be low, as shown in Table 3. Make

sure the DOUT bus does not drive heavy loads (>

20pF), as this will degrade performance. Use an exter-

nal buffer when driving an edge connector or cables.

Table 3. Truth Table for CS and RD

DOUT[15:0]

Active

High impedance

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