7

Supertex inc.

www.supertex.com

MD3872

Doc.# DSFP-MD3872

B060413

ADDR=0 D[7:2]

OUTDLY[5:0] LVDS ADC Data Output Delay Adjustment Table

OUTDLY[5:0]

Typical Rise Time Delay (ps)

Typical Fall Time Delay (ps)

00 0000

655

685

00 0001

766

805

… …

DELAY = 139.4 x FDDLY +655

DELAY = 148.5 x FDDLY + 699

11 1110

9241

9824

11 1111

9340

9951

Note:

OUTDLY[5:0] and ADDR = D, FDDLY[5:0] are for LVDS data OUT8-1, DCLK and FCLK alignment delay time setting.

ADDR=0 D[1:0]

ATP[1:0] LVDS Alignment Test Pattern Control Table

D1

D0

LVDS Output Description

0

0

Latest ADC Results.

0

1

TPDC[11:0] data written in ADDR[C], the LVDS testing data #C.

1

0

Fixed predefined test pattern: “1000 0000 0000”

1

1

TPD1[11:0] data written in ADDR[1], the LVDS testing data #1.

ADDR=0 D[10:8]

STEP[2:0] LVDS Delay Step Size Control Table

STEP[2:0]

Delay Time Step Size

000

100% (Default value)

120ps

001

133%

160ps

010

200%

240ps

011

400%

480ps

100

50% (min)

60ps

101

57%

69ps

110

67%

80ps

111

80%

96ps

Note:

1. LDVS delay time step size control. Each bit will change the delay step size by 120ps. Setting a different value

than 00 will change the DLOUT[5:0] and FDDLY[5:0] delay-time’s step-size.

2. If f

TGC and GSC Voltage for Gain Scaling LNA Feedback Configurations

0

1.7

Minimum Slope

Maximum Slope

TGC Voltage (V)

-47

0

R

S

C

IN+

C

f

R

f1

LNA

SW

C

IN-

VGA

IN+

IN-

R

f2

PA-

+

-