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MD3872 Scheda tecnica(PDF) 5 Page - Supertex, Inc

Il numero della parte MD3872
Spiegazioni elettronici  Low Power, Low Noise Ultrasound Receive Front-End Eight-Channels of LNA, VGA, AAF, CPS & 12-Bit, 50MHz ADCs
PDF  24 Pages
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Produttore elettronici  SUTEX [Supertex, Inc]
Homepage  http://www.supertex.com
Logo SUTEX - Supertex, Inc

MD3872 Scheda tecnica(HTML) 5 Page - Supertex, Inc

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Supertex inc.
www.supertex.com
MD3872
Doc.# DSFP-MD3872
B060413
Internal and External Reference Characteristics
(Over operating conditions unless otherwise specified, AV
DD = DVDD= 1.8V, CWVDD =+3.3V, RSEL = Hi, RS = 50Ω, TA = 25°C)
Sym
Parameter
Min
Typ
Max
Unit
Conditions
V
REF+
ADC reference top voltage
-
1.4
-
V
ADC reference voltages, decou-
pling capacitors required
V
REF-
ADC reference bottom voltage
-
0.4
-
V
V
REF_EXT
External reference voltage
-
1.0
-
V
EXT = Hi (select external V
REF)
I
REF_MAX
Max reference output current
-
1.0
-
mA
---
CW Doppler Mode Characteristics
(Over operating conditions unless otherwise specified, AV
DD = DVDD= 1.8V, CWVDD =+3.3V, RSEL = Hi, RS = 50Ω, TA = 25°C)
g
m
Transconductance
-
9.5/15.2
-
mA/V
LNA Gain = 14/18dB
V
COMM
Common-mode voltage
1.5
-
3.6
V
CW Doppler output pins
V
CW-NOISE
Input-referred noise voltage
-
1.75/1.45
-
nV/√Hz LNA Gain 14/18dB, R
S = 0, RFB = ∞
I
OUT-BIAS
Output DC bias
-
2.8
-
mA
Per channel
I
OUT-SWING
Maximum output swing
-
±2.3
-
mA
P-P
---
Switching AC Characteristics
(Over operating conditions unless otherwise specified, AV
DD = DVDD= 1.8V, CWVDD =+3.3V, RSEL = Hi, RS = 50Ω, TA = 25°C)
F
S
ADC conversion rate
20
-
50
MSPS
---
t
S
Clock period
20
-
50
ns
---
t
CLKWH
Clock pulse-width high
-
12.5
-
ns
---
t
CLKWL
Clock pulse-width low
-
12.5
-
ns
---
t
PRP
ADC clock propagation delay
-
2.6
-
ns
---
PL
d
Pipeline latency delay
-
5.5
-
cycle
---
t
SBY_DWN
Time to standby
-
1.0
-
µs
---
t
SBY_WUP
Time to wakeup
-
10
-
µs
---
t
PD_DWN
Time to power down
-
1.0
-
µs
---
t
PD_UP
Time to power up
-
10
-
ms
---
t
1
SDI valid to SCK setup time
0
2.0
-
ns
See serial interface timing diagram
t
2
SDI valid to SCK hold time
4.0
-
-
t
3
SCK high time
9.0
10
-
t
4
SCK low time
9.0
10
-
t
5
CSB pulse width
9.0
10
-
t
6
SCK high to CSB low
-
4.5
-
f
SCK
Serial clock max frequency
50
-
-
MHz
---



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