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MD3872 Scheda tecnica(PDF) 6 Page - Supertex, Inc

Il numero della parte MD3872
Spiegazioni elettronici  Low Power, Low Noise Ultrasound Receive Front-End Eight-Channels of LNA, VGA, AAF, CPS & 12-Bit, 50MHz ADCs
PDF  24 Pages
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Produttore elettronici  SUTEX [Supertex, Inc]
Homepage  http://www.supertex.com
Logo SUTEX - Supertex, Inc

MD3872 Scheda tecnica(HTML) 6 Page - Supertex, Inc

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Supertex inc.
www.supertex.com
MD3872
Doc.# DSFP-MD3872
B060413
Level
ADC Input Voltage
Binary Digital Output
Notes
4094
V
IN > +0.999756V
1111 1111 1110
---
...
...
...
---
2048
+0.000244V < V
IN < +0.000732V
1000 0000 0000
---
2047
-0.000244V < V
IN < +0.000244V
0111 1111 1111
---
...
...
...
---
0
V
IN < -0.999756V
0000 0000 0000
---
12-Bit ADC Digital Output Coding Table
SPI Registers Address and Data Table
MSB (shift in first)
SPI Register Data Word
LSB
ADDR[3:0]
Hex
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
-
STEP[2:0]
(Alignment Step Size)
OUTDLY[5:0]
(All channel OUTLVDS alignment delay setting)
ATP[1:0]
1
TPD1[11:0] (LVDS Testing Pattern #1)
2
CW1[5:0] (Channel 1 CW mode control)
CW2[5:0] (Channel 2 CW mode control)
3
CW3[5:0] (Channel 3 CW mode control)
CW4[5:0] (Channel 4 CW mode control)
4
CW5[5:0] (Channel 5 CW mode control)
CW6[5:0] (Channel 6 CW mode control)
5
CW7[5:0] (Channel 7 CW mode control)
CW8[5:0] (Channel 8 CW mode control)
6
-
-
-
CW/
TGC
CHOFF[7:0] (TGC Per Channel Power Off, 0=ON 1=OFF)
7
-
-
AAF[1:0]
-
PDC
FLEX
-
SWLNA GAIN-
LNA
PG[1:0]
8
-
-
CTL
PR[5:2]
-
AAF[5:2]
9
-
-
-
-
ADCPD[7:0] (ADC Per Channel Power Down, 0 = ON 1 = OFF)
A
-
-
-
-
Reserved Default all 0
B
SWING[2:0]
-
Reserved Default all 0
C
TPDC[11:0] (LVDS Testing Pattern #C)
D
FDDLY[5:0] (FCLK and DCLK alignment delay setting)
-
-
-
-
-
-
E
Reserved Default all 0
F
ADDR[3:0] to READ Back
-
-
-
-
-
-
-
-
Note:
A bit marked as “-“ means do-not-care whether it is set to “1” or “0”.



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