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AX2000 Scheda tecnica(PDF) 35 Page - Microsemi Corporation

Il numero della parte AX2000
Spiegazioni elettronici  Axcelerator Family FPGAs
PDF  262 Pages
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Produttore elettronici  MICROSEMI [Microsemi Corporation]
Homepage  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

AX2000 Scheda tecnica(HTML) 35 Page - Microsemi Corporation

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Axcelerator Family FPGAs
Re vi s i on 18
2 - 21
I/O Standard Electrical Specifications
Table 2-18 • Input Capacitance
Symbol
Parameter
Conditions
Min.
Max.
Units
CIN
Input Capacitance
VIN = 0, f = 1.0 MHz
10
pF
CINCLK
Input Capacitance on HCLK and RCLK Pin
VIN = 0, f = 1.0 MHz
10
pF
Table 2-19 • I/O Input Rise Time and Fall Time*
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
LVTTL
No Requirement
50 ns
LVCMOS 2.5V
No Requirement
50 ns
LVCMOS 1.8V
No Requirement
50 ns
LVCMOS 1.5V
No Requirement
50 ns
PCI
No Requirement
50 ns
PCIX
No Requirement
50 ns
GTL+
No Requirement
50 ns
HSTL
No Requirement
50 ns
SSTL2
No Requirement
50 ns
HSTL3
No Requirement
50 ns
LVDS
No Requirement
50 ns
LVPECL
No Requirement
50 ns
Note:
*Input Rise/Fall time applies to all inputs, be it clock or data. Inputs have to ramp up/down linearly,
in a monotonic way. Glitches or a plateau may cause double clocking. They must be avoided. For
output rise/fall time, refer to the IBIS models for extraction.
Figure 2-9 •
Input Buffer Delays
Y
IN
INBUF
PAD
ln
Y
GND
Input High
0 V
VCCA
tDP
tDP
VTRIP
VTRIP
50%
50%
(Rising)
(Falling)



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