AX2000 datasheet(12/262 Pages) MICROSEMI

12 / 262 page

General Description

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Global Resources

Each family member has three types of global signals available to the designer: HCLK, CLK, and

GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input

of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an

R-cell or any input of a C-cell (Figure 1-3 on page 1-2).

Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well

as each I/O Register on a chip-wide basis at power-up.

Each HCLK and CLK has an associated analog PLL (a total of eight per chip). Each embedded PLL can

be used for clock delay minimization, clock delay adjustment, or clock frequency synthesis. The PLL is

capable of operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output

frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by factors ranging

from 1 to 64. Additionally, multiply and divide settings can be used in any combination as long as the

resulting clock frequency is between 20 MHz and 1 GHz. Adjacent PLLs can be cascaded to create

complex frequency combinations.

The PLL can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps

increments. The reference clock required to drive the PLL can be derived from three sources: external

input pad (either single-ended or differential), internal logic, or the output of an adjacent PLL.

Low Power (LP) Mode

The AX architecture was created for high-performance designs but also includes a low power mode

(activated via the LP pin). When the low power mode is activated, I/O banks can be disabled (inputs

disabled, outputs tristated), and PLLs can be placed in a power-down mode. All internal register states

are maintained in this mode. Furthermore, individual I/O banks can be configured to opt out of the LP

mode, thereby giving the designer access to critical signals while the rest of the chip is in low power

mode.

The power can be further reduced by providing an external voltage source (VPUMP) to the device to

bypass the internal charge pump (See "Low Power Mode" on page 2-106 for more information).

Figure 1-8 •

AX Routing Structures

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