AX2000 datasheet(100/262 Pages) MICROSEMI

100 / 262 page

Detailed Specifications

2- 86

R e v i sio n 1 8

Embedded Memory

The AX architecture provides extensive, high-speed memory resources to the user. Each 4,608 bit block

of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either

RAM or FIFO.

To meet the needs of high performance designs, the memory blocks operate in synchronous mode for

both read and write operations. However, the read and write clocks are completely independent, and

each may operate up to and above 500 MHz.

No additional core logic resources are required to cascade the address and data buses when cascading

different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading.

The AX memory block includes dedicated FIFO control logic to generate internal addresses and external

flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously

to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A

block diagram of the memory module is illustrated in Figure 2-57.

During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO

controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and

routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create

upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed

signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion.

Figure 2-57 • Axcelerator Memory Module

RA [K:0]

RD [(N-1):0]

REN

RCLK

WD [(M-1):0]

WA [J:0]

WEN

WCLK

PIPE

RW [2:0]

WW [2:0]

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