R5F110PH datasheet(43/153 Pages) RENESAS

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RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 43 of 149

Feb 21, 2014

2.5

Peripheral Functions Characteristics

AC Timing Test Points

2.5.1

Serial array unit

Note 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

Note 2.

The following conditions are required for low voltage interface.

2.4 V

 VDD < 2.7 V: MAX. 2.6 Mbps

1.8 V

 VDD < 2.4 V: MAX. 1.3 Mbps

1.6 V

 VDD < 1.8 V: MAX. 0.6 Mbps

Note 3.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V

 VDD  3.6 V)

16 MHz (2.4 V

 VDD  3.6 V)

LS (low-speed main) mode:

8 MHz (1.8 V

 VDD  3.6 V)

LV (low-voltage main) mode:

4 MHz (1.6 V

 VDD  3.6 V)

Caution

Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input

mode register g (PIMg) and port output mode register g (POMg).

(1)

During communication at same potential (UART mode)

(TA = -40 to +85 °C, 1.6 V  VDD  3.6 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

LS (low-speed main)

Mode

LV (low-voltage main)

Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer

rate Note 1

2.7 V

 VDD  3.6 V

fMCK/6 Note 2

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 3

4.0

1.3

0.6

Mbps

2.4 V

 VDD  3.6 V

fMCK/6 Note 2

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 3

2.6

1.3

0.6

Mbps

1.8 V

 VDD  3.6 V

—

fMCK/6 Note 2

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 3

—

1.3

0.6

Mbps

1.6 V

 VDD  3.6 V

—

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK Note 3

—

0.6

Mbps

VIH/VOH

VIL/VOL

VIH/VOH

Test points

VIL/VOL

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