R5F110PH datasheet(45/153 Pages) RENESAS

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RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 45 of 149

Feb 21, 2014

Note 1.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 2.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 3.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from

SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 4.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 2)

Remark 2.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00))

(2)

During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,

corresponding CSI00 only)

(TA = -40 to +85 °C, 2.7 V  VDD  3.6 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

LS (low-speed main)

Mode

LV (low-voltage main)

Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

 fCLK/2

2.7 V

 VDD  3.6 V

167

250

500

SCKp high-/

low-level width

tKL1

2.7 V

 VDD  3.6 V

tKCY1/2 - 10

tKCY1/2 - 50

SIp setup time

(to SCKp

↑) Note 1

tSIK1

2.7 V

 VDD  3.6 V

110

SIp hold time

(from SCKp

↑) Note 2

tKSI1

2.7 V

 VDD  3.6 V

Delay time from

SCKp

↓ to SOp

output Note 3

tKSO1

C = 20 pF Note 4

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