DP83849CVSSLASHNOPB datasheet(23/101 Pages) TI1

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3.0 MAC Interface

The DP83849C supports several modes of operation using

the MII interface pins. The options are defined in the follow-

ing sections and include:

— MII Mode

— RMII Mode

— 10 Mb Serial Network Interface (SNI)

The modes of operation can be selected by strap options

or register control. For RMII mode, it is required to use the

strap option, since it requires a 50 MHz clock instead of the

normal 25 MHz.

In each of these modes, the IEEE 802.3 serial manage-

ment interface is operational for device configuration and

status. The serial management interface of the MII allows

for the configuration and control of multiple PHY devices,

gathering of status, error information, and the determina-

tion of the type and capabilities of the attached PHY(s).

3.1 MII Interface

The DP83849C incorporates the Media Independent Inter-

face (MII) as specified in Clause 22 of the IEEE 802.3u

standard. This interface may be used to connect PHY

devices to a MAC in 10/100 Mb/s systems. This section

describes the nibble wide MII data interface.

The nibble wide MII data interface consists of a receive bus

and a transmit bus each with control signals to facilitate

data transfer between the PHY and the upper layer (MAC).

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the

Media Independent Interface. This interface includes a

dedicated receive bus and a dedicated transmit bus. These

two data buses, along with various control and status sig-

nals, allow for the simultaneous exchange of data between

the DP83849C and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus

RXD[3:0], a receive error signal RX_ER, a receive data

valid flag RX_DV, and a receive clock RX_CLK for syn-

chronous transfer of the data. The receive clock operates

at either 2.5 MHz to support 10 Mb/s operation modes or at

25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus

TXD[3:0], a transmit enable control signal TX_EN, and a

transmit clock TX_CLK which runs at either 2.5 MHz or 25

MHz.

Additionally, the MII includes the carrier sense signal CRS,

as well as a collision detect signal COL. The CRS signal

asserts to indicate the reception of data from the network

or as a function of transmit data in Half Duplex mode. The

COL signal asserts as an indication of a collision which can

occur during half-duplex operation when both a transmit

and receive operation occur simultaneously.

3.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is

detected when the receive and transmit channels are

active simultaneously. Collisions are reported by the COL

signal on the MII.

If the DP83849C is transmitting in 10 Mb/s mode when a

collision is detected, the collision is not reported until seven

bits have been received while in the collision state. This

prevents a collision being reported incorrectly due to noise

on the network. The COL signal remains set for the dura-

tion of the collision.

If a collision occurs during a receive operation, it is immedi-

ately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s

operation), approximately 1

µs after the transmission of

each packet, a Signal Quality Error (SQE) signal of approx-

imately 10 bit times is generated (internally) to indicate

successful transmission. SQE is reported as a pulse on the

COL signal of the MII.

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity,

once valid data is detected via the squelch function during

10 Mb/s operation. During 100 Mb/s operation CRS is

asserted when a valid link (SD) and two non-contiguous

zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted

during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted

only due to receive activity.

CRS is deasserted following an end of packet.

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