DP83849CVSSLASHNOPB datasheet(24/101 Pages) TI1

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3.2 Reduced MII Interface

The DP83849C incorporates the Reduced Media Indepen-

dent Interface (RMII) as specified in the RMII specification

(rev1.2) from the RMII Consortium. This interface may be

used to connect PHY devices to a MAC in 10/100 Mb/s

systems using a reduced number of pins. In this mode,

data is transferred 2-bits at a time using the 50 MHz

RMII_REF clock for both transmit and receive. The follow-

ing pins are used in RMII mode:

—TX_EN

—TXD[1:0]

— RX_ER (optional for Mac)

— CRS_DV

— RXD[1:0]

— X1 (RMII Reference clock is 50 MHz)

In addition, the RMII mode supplies an RX_DV signal

which allows for a simpler method of recovering receive

data without having to separate RX_DV from the CRS_DV

indication. This is especially useful for diagnostic testing

where it may be desirable to externally loop Receive MII

data directly to the transmitter.

The RX_ER output may be used by the MAC to detect

error conditions. It is asserted for symbol errors received

during a packet, False Carrier events, and also for FIFO

underrun or overrun conditions. Since the Phy is required

to corrupt receive data on an error, a MAC is not required

to use RX_ER.

It is important to note that since both digital channels in the

DP83849C share the X1/RMII_REF input, both channels

must have RMII mode enabled or both channels must have

RMII mode disabled. Either channel may be in 10Mb or

100Mb mode in RMII or non-RMII mode.

Since the reference clock operates at 10 times the data

rate for 10 Mb/s operation, transmit data is sampled every

10 clocks. Likewise, receive data will be generated every

10th clock so that an attached device can sample the data

every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to

the device X1 pin. A 50 MHz crystal is not supported.

To tolerate potential frequency differences between the 50

MHz reference clock and the recovered receive clock, the

receive RMII function includes a programmable elasticity

buffer. The elasticity buffer is programmable to minimize

propagation delay based on expected packet size and

clock accuracy. This allows for supporting a range of

packet sizes including jumbo frames.

The elasticity buffer will force Frame Check Sequence

errors for packets which overrun or underrun the FIFO.

Underrun and Overrun conditions can be reported in the

RMII and Bypass Register (RBR). The following table indi-

cates how to program the elasticity buffer fifo (in 4-bit incre-

ments) based on expected max packet size and clock

accuracy. It assumes both clocks (RMII Reference clock

and far-end Transmitter clock) have the same accuracy.

Packet lengths can be scaled linearly based on accuracy

(+/- 25ppm would allows packets twice as large). If the

threshold setting must support both 10Mb and 100Mb

operation, the setting should be made to support both

speeds.

Table 4. Supported packet sizes at +/-50ppm frequency accuracy

Start Threshold

RBR[1:0]

Latency Tolerance

Recommended Packet Size

at +/- 50ppm

100Mb

10Mb

100Mb

10Mb

01 (default)

2 bits

8 bits

2,400 bytes

9,600 bytes

6 bits

4 bits

7,200 bytes

4,800 bytes

10 bits

8 bits

12,000 bytes

9,600 bytes

14 bits

12 bits

16,800 bytes

14,400 bytes

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