DP83849CVSSLASHNOPB datasheet(43/101 Pages) TI1

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6.0 Reset Operation

The DP83849C includes an internal power-on reset (POR)

function and does not need to be explicitly reset for normal

operation after power up. If required during normal opera-

tion, the device can be reset by a hardware or software

reset.

6.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse

(TTL level), with a duration of at least 1

µs, to the

RESET_N pin. This will reset the device such that all regis-

ters will be reinitialized to default values and the hardware

configuration values will be re-latched into the device (simi-

lar to the power-up/reset operation).

6.2 Full Software Reset

A full-chip software reset is accomplished by setting the

reset bit (bit 15) of the Basic Mode Control Register

(BMCR). The period from the point in time when the reset

bit is set to the point in time when software reset has con-

cluded is approximately 1

µs.

The software reset will reset the device such that all regis-

ters will be reset to default values and the hardware config-

uration values will be maintained. Software driver code

must wait 3

µs following a software reset before allowing

further serial MII operations with the DP83849C.

6.3 Soft Reset

A partial software reset can be initiated by setting the Soft

Reset bit (bit 9) in the PHYCR2 Register. Setting this bit will

reset all transmit and receive operations, but will not reset

the register space. All register configurations will be pre-

served. Register space will remain available following a

Soft Reset.

DP83849CVS/NOPB Scheda tecnica(PDF) 43 Page - Texas Instruments