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GMS81C2012 Scheda tecnica(PDF) 33 Page - Hynix Semiconductor |
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GMS81C2012 Scheda tecnica(HTML) 33 Page - Hynix Semiconductor |
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33 / 107 page  HYUNDAI MicroElectronics GMS81C2012/GMS81C2020 MAR. 2000 Ver 1.00 33 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C2H R1 R1 Port Data Register (Bit[7:0]) C3H R1IO R1 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[5:0]) C7H R3IO R3 Port Direction Register (Bit[5:0]) C8H R4 R4 Port Data Register (Bit[3:0]) C9H R4IO R4 Port Direction Register (Bit[3:0]) CAH R5 R5 Port Data Register (Bit[7:0]) CBH R5IO R5 Port Direction Register (Bit[7:0]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) CEH R7 R7 Port Data Register (Bit[5:0]) CFH R7IO R7 Port Direction Register (Bit[5:0]) D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Capture0 Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR SPI DATA REGISTER E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register Table 8-3 Control Registers of GMS81C2020 These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by reg- ister operation instruction as " LDM dp,#imm ". |
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