GMS81C2012 datasheet(66/107 Pages) HYNIX

66 / 107 page

GMS81C2012/GMS81C2020

HYUNDAI MicroElectronics

MAR. 2000 Ver 1.00

Serial I/O Mode Register(SIOM) controls serial I/O func-

tion. According to SCK1 and SCK0, the internal clock or

external clock can be selected. The serial transmission op-

eration mode is decided by setting the SM1 and SM0, and

the polarity of transfer clock is selected by setting the POL.

Serial I/O Data Register(SIOR) is a 8-bit shift register.

First LSB is send or is received. When receiving mode, se-

rial input pin is selected by IOSW. The SPI allows 8-bits

of data to be synchronously transmitted and received.

To accomplish communication, typically three pins are

used:

- Serial Data In

R54/SIN

- Serial Data Out

R55/SOUT

- Serial Clock

R53/SCLK

Figure 14-2 SPI Control Register

BTCL

765

432

IOSW

POL

SIOST

Serial transmission status bit

Serial transmission Clock selection

INITIAL VALUE: 0000 0001B

ADDRESS: 0E0H

SIOM

SIOSF

Serial Input Pin Selection bit

0: SIN Pin Selection

1: IOSWIN Pin Selection

R/W

00: fXIN ÷ 4

01: fXIN ÷ 16

10: TMR0OV(Timer0 Overflow)

11: External Clock

0: Serial transmission is in progress

1: Serial transmission is completed

Serial transmission start bit

Setting this bit starts an Serial transmission.

After one cycle, bit is cleared to “0” by hardware.

SCK1 SCK0

SM1

SM0

R/W

Serial transmission Operation Mode

00: Normal Port(R55,R54,R53)

01: Sending Mode(SOUT,R54,SCLK)

10: Receiving Mode(R55,SIN,SCLK)

11: Sending & Receiving Mode(SOUT,SIN,SCLK)

INITIAL VALUE: Undefined

ADDRESS: 0E1H

SIOR

BTCL

R/W R/W R/W R/W

R/W R/W

R/W

Sending Data at Sending Mode

Receiving Data at Receiving Mode

Serial Clock Polarity Selection bit

0: Data Transmission at Falling Edge

Received Data Latch at Rising Edge

1: Data Transmission at Rising Edge

Received Data Latch at Falling Edge

R/W

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