28F016SA datasheet(17/55 Pages) INTEL

17 / 55 page

28F016SA

NOTES:

RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps.

Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the

actual lock-bit status.

A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL.

The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the

Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page

Buffer expandability.

In x16 mode, only the lower byte DQ0–7 is used for WCL and WCH. The upper byte DQ8–15 is a don’t care.

PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

This command allows the user to swap between available Page Buffers (0 or 1).

These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

Program address, PA, is the destination address in the flash array which must match the source address in the Page

Buffer. Refer to the

16-Mbit Flash Product Family User’s Manual.

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the 28F016SA’s power consumption during sleep mode reaches the deep power-down current level, the

system also needs to de-select the chip by taking either or both CE0# or CE1# high.

12. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.

28F016SA Scheda tecnica(PDF) 17 Page - Intel Corporation