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28F016SA Scheda tecnica(PDF) 3 Page - Intel Corporation |
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28F016SA Scheda tecnica(HTML) 3 Page - Intel Corporation |
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3 / 55 page ![]() E 28F016SA 3 CONTENTS PAGE PAGE 1.0 INTRODUCTION ............................................. 5 1.1 Product Overview ........................................ 5 2.0 DEVICE PINOUT............................................. 6 2.1 Lead Descriptions ........................................ 8 3.0 MEMORY MAPS ........................................... 12 3.1 Extended Status Register Memory Map..... 13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 14 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)........................................... 14 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) ........................................... 14 4.3 28F008SA–Compatible Mode Command Bus Definitions.......................................... 15 4.4 28F016SA–Performance Enhancement Command Bus Definitions......................... 16 4.5 Compatible Status Register ....................... 18 4.6 Global Status Register ............................... 19 4.7 Block Status Register ................................ 20 5.0 ELECTRICAL SPECIFICATIONS ................. 21 5.1 Absolute Maximum Ratings ....................... 21 5.2 Capacitance............................................... 22 5.3 Timing Nomenclature................................. 23 5.4 DC Characteristics (VCC = 3.3V ± 10%) ..... 26 5.5 DC Characteristics (VCC = 5.0V ± 10%, 5.0V ± 5%) ................ 29 5.6 AC Characteristics–Read Only Operations.................................................32 5.7 Power-Up and Reset Timings.....................37 5.8 AC Characteristics for WE#–Controlled Command Write Operations ......................38 5.9 AC Characteristics for CE#–Controlled Command Write Operations ......................42 5.10 AC Characteristics for Page Buffer Write Operations.................................................46 5.11 Erase and Word/Byte Program Performance, Cycling Performance and Suspend Latency.......................................49 6.0 DERATING CURVES.....................................50 7.0 MECHANICAL SPECIFICATIONS FOR TSOP ............................................................52 8.0 MECHANICAL SPECIFICATIONS FOR SSOP............................................................53 APPENDIX A: Device Nomenclature and Ordering Information ..................................54 APPENDIX B: Additional Information ...............55 |
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