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28F016SA Scheda tecnica(PDF) 23 Page - Intel Corporation |
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28F016SA Scheda tecnica(HTML) 23 Page - Intel Corporation |
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23 / 55 page ![]() E 28F016SA 23 5.3 Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of five characters. Some common examples are defined below: tCE tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tOE tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V) tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAS tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tDH tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters Pin States A Address Inputs H High D Data Inputs L Low Q Data Outputs V Valid E CE# (Chip Enable) X Driven, but not necessarily valid F BYTE# (Byte Enable) Z High Impedance G OE# (Output Enable) W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V Any Voltage Level Y 3/5# Pin 5V VCC at 4.5V Minimum 3V VCC at 3.0V Minimum |
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