AN4671 datasheet(9/17 Pages) STMICROELECTRONICS

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AN4671

How to minimize switching losses

DocID027654 Rev 1

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2.3

Miller effect on Eon and Err

A voltage change, dvDS/dt, occurs across the upper switch when turning on the low-side

MOSFET in a half-bridge. This creates a current which charges the parasitic capacitance

CGD of the upper MOSFET; this current flows via the Miller capacitance, the gate resistor

and the CGS (capacitances CGD and CGS form a capacitive voltage divider). If the voltage

drop across the gate resistor exceeds the threshold voltage of the upper MOSFET, a

parasitic turn-on known as ‘Miller turn-on’ or ‘Miller effect’ occurs, which can significantly

impact overall leg switching losses. Parasitic turn-on may also occur when the high-side

MOSFET is switched-on and a current flows through the Miller capacitance of the lower

switch.

The SiC MOSFET is also affected by this phenomenon. In the test circuit below, the

SCT30N120 implementing the high-side switch is kept off by a negative supply voltage

applied across the gate and source (Voff-HS is in the 0 to -10 V range) in series with the

turn-off gate resistor (Roff-HS).

The turn-on of the low side switch, also implemented by the SCT30N120, causes the

dvDS/dt across the HS switch. Gate resistors Roff-LS and Ron-LS are connected to the gate of

the LS MOSFET to manage turn-off and turn-on switching. The test circuit below shows

how the HS MOSFET Miller turn-on negatively affects the LS MOSFET Eon.

Figure 8: Miller turn-on test circuit

Analysis of the Miller turn-on phenomenon involves investigating how the low-side Eon and

high-side Err vary with Roff-HS, Ron-LS and Voff-HS.

Err is the switching energy dissipated by the SiC MOSFET after the conduction of its

intrinsic body diode. In the absence of the Miller effect, it is negligible due to the excellent

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