Low-Cost Precision Sensor

Signal Conditioner

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Table 8. Control Location (CL[15:0])

FIELD

NAME

DESCRIPTION

15:8

CL[15:8]

Reserved

7:0

CL[7:0]

Control Location. Secure-Lock is activated by setting this to FFhex which disables DIO serial

communications and connects OUT to PGA output.

Table 9. IRSA Decoding

IRSA[3:0]

DESCRIPTION

0000

Write IRSD[3:0] to DHR[3:0] (data hold register)

0001

Write IRSD[3:0] to DHR[7:4] (data hold register)

0010

Write IRSD[3:0] to DHR[11:8] (data hold register)

0011

Write IRSD[3:0] to DHR[15:12] (data hold register)

0100

Reserved

0101

Reserved

0110

Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0], (internal calibration register address or internal EEPROM address

nibble 0)

0111

Write IRSD[3:0] to IEEA[7:4] (internal EEPROM address, nibble 1)

1000

Write IRSD[3:0] to IRSP[3:0] or IEEA[9:8], (interface register set pointer where IRSP[1:0] is IEEA[9:8])

1001

Write IRSD[3:0] to CRIL[3:0] (command register to internal logic)

1010

Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read)

1011

Write IRSD[3:0] to ALOC[3:0] (analog location)

1100 to 1110

Reserved

1111

Write IRSD[3:0] = 1111bin to relearn the baud rate