A25LQ64 datasheet(10/70 Pages) AMICC

10 / 70 page

A25LQ64 Series

(July, 2014, Version 1.4)

AMIC Technology Corp.

Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad

I/O Serial Flash by providing the Quad I/O interface in

command cycles, address cycles and as well as data output

cycles.

Enable QPI mode (EQIO)

By issuing 35H command, the QPI mode is enable.

Figure 2. Enable QPI Sequence (Command 35H)

IO0

IO[3:1]

0 1 23 45 6 7

35h

MODE 3

MODE 0

Quad Peripheral Interface (QPI) operation

To use QPI protocol, the host drives S low then sends the

Fast Read command, 0BH, followed by 6 address cycles and

four dummy cycles. Most significant bit (MSB) comes first, as

shown in figure 3.

After the dummy cycle, the Quad Peripheral Interface (QPI)

Flash Memory outputs data on the falling edge of the Serial

Clock (C) signal starting from the specified address location.

The device continually streams data output through all

addresses until terminated by a low-to-high transition on S .

The internal address pointer automatically increases until the

highest memory address is reached. When reached the

highest memory address, the address pointer returns to the

beginning of the address space.

Figure 3. High-Speed Read Sequence (QPI) (Command 0BH)

01 2 3

5 6 7

48 9 10 11

13 14 15

16 17 18

IO[3:0]

A2 A1 A0 XXXX H0 L0 H1 L1 H2 L2 H3 L3

Data In

MSB

Data Out

MODE 3

MODE 0

MODE 3

MODE 0

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