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A25LQ64 Scheda tecnica(PDF) 2 Page - AMIC Technology

Il numero della parte A25LQ64
Spiegazioni elettronici  64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO
PDF  70 Pages
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Produttore elettronici  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A25LQ64 Scheda tecnica(HTML) 2 Page - AMIC Technology

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A25LQ64 Series
64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO
(SERIAL MULTI I/O) FLASH MEMORY
(July, 2014, Version 1.4)
1
AMIC Technology Corp.
FEATURES
GENERAL
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits
(two I/O mode) structure or 16,777,216 x 4 bits (four I/O
mode) structure
Equal Sectors with 4K byte each, or Equal Blocks with
32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to VCC +1V
Low VCC write inhibit is from 2.2V to 2.4V
PERFORMANCE
High Performance
- Fast read for SPI mode
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to
416MHz
- Fast read for QPI mode
- 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to
336MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to
416MHz
- Fast program time: 0.3ms (typ.) and 0.8ms (max./10K)/
2ms (max./100K) /page (256-byte per page)
- Byte program time: 6
μs (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
-Fast erase time: 40ms (typ.)/sector (4K-byte per sector);
80ms (typ.)/block (32K-byte per block), 120ms (typ.) /
block (64K-byte per block); 12s(typ.) /chip
Low Power Consumption
- Low active read current: 25mA (max.) at 104MHz, 20mA
(max.) at 84MHz
- Low active erase/programming current: 20mA (typ.)
- Standby current: 2
μA (typ.)
Deep Power Down: 2
μA(typ.)
Typical 100,000 erase/program cycles
10 years data retention
SOFTWARE FEATURES
Input Data Format
- 1-byte Command code
Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to
be software protection against program and erase
instructions
- Additional 4k-bit secured OTP
- 1K bit SFDP serial flash definition parameter
- 64 bytes unique ID for each device
Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
or block
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programmed
should have page in the erased state first)
Status Register Feature
Command Reset
Program/Erase Suspend
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte
device ID
When using A25LQ64M-FE, the Hardware Protected
Mode (HPM) is disabled
HARDWARE FEATURES
Serial Clock (C)
- Serial clock input
DI (IO0)
- Serial Data Input or Serial Data Input/Output for 2 x I/O
read mode and 4 x I/O read mode
DO (IO1)
- Serial Data Output or Serial Data Input/Output for 2 x I/O
read mode and 4 x I/O read mode
W (IO2)
- Hardware write protection or serial data Input/Output for
4 x I/O read mode
IO3
- Serial input & Output for 4 x I/O read mode
PACKAGE
- 8-pin DIP (300mil), 8-pin SOP (209mil), 16-pin SOP
(300mil), 8-pin WSON (6*5mm) or 24-ball BGA
(6*8mm)
- All Pb-free (Lead-free) products are RoHS2.0 compliant



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