A25LQ64 datasheet(39/70 Pages) AMICC

39 / 70 page

A25LQ64 Series

(July, 2014, Version 1.4)

AMIC Technology Corp.

Table 12. AC Characteristics (TA = -40°C to 85°C, VCC = 2.6V ~ 3.7V)

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions: FAST READ, PP,

4PP, SE, BE, CE, DP, RES, RDP WREN, WRDI, RDID, RDSR,

WRSR

D.C.

104

MHz

fRC

Clock Frequency for READ instructions

MHz

Clock Frequency for 2READ instructions

MHz

fTC

Clock Frequency for 4READ instructions

(5)

84/104

MHz

Serial (fC)

4.5

tCH

(1)(2)

tCLH

Clock High Time

4PP and Normal Read (fRC)

4.5

Serial (fC)

4.5

tCL

(1)(2)

tCLL

Clock Low Time

4PP and Normal Read (fRC)

4.5

tCLCH

(2)

Clock Rise Time

(3) (peak to peak)

0.1

V/ns

tCHCL

(2)

Clock Fall Time

(3) (peak to peak)

0.1

V/ns

tSLCH

(2)

tCSS

S Active Setup Time (relative to C)

tCHSL

(2)

S Not Active Hold Time (relative to C)

tDVCH

tDSU

Data In Setup Time

tCHDX

(2)

tDH

Data In Hold Time

tCHSH

S Active Hold Time (relative to C)

tSHCH

S Not Active Setup Time (relative to C)

Read

tSHSL

(3)

tCSH

S Deselect Time

Write/Erase/Program

tSHQZ

(2)

tDIS

Output Disable Time

Loading: 30pF

tCLQV

Clock Low to Output Valid

Loading: 30pF/15pF

Loading: 15pF

tCLQX

tHO

Output Hold Time

tWHSL

Write Protect Setup Time

tSHWL

Write Protect Hold Time

100

tDP

(2)

S High to Deep Power-down Mode

μs

tRES1

(2)

S High to Standby Mode without Electronic Signature Read

μs

tRES2

(2)

S High to Standby Mode with Electronic Signature Read

μs

tRCR

Recovery Time from Read

μs

tRCP

Recovery Time from Program

μs

tRCE

Recovery Time from Erase

Write Status Register Cycle Time

tBP

Byte-Program

μs

tPP

Page Program Cycle Time

0.3

0.8/2

(6)

tSE

Sector Erase Cycle Time

150

tBE32

Block Erase (32KB) Cycle Time

300

tBE

Block Erase (64KB) Cycle Time

120

500

tCE

Chip Erase Cycle Time

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Value guaranteed by characterization, not 100% tested in production.

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Test condition is shown as Figure 11.

5. When dummy cycle=4 (In both QPI & SPI mode), clock rate=84MHz; when dummy cycle=6 (In both QPI & SPI mode), clock

rate=104MHz.

6. The page program time is 0.8ms(max.) after 10K cycling and 2ms(max.) after 100K cycling.

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