A25LQ64 datasheet(21/70 Pages) AMICC

21 / 70 page

A25LQ64 Series

(July, 2014, Version 1.4)

AMIC Technology Corp.

Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status

Enable (WREN) instruction must be decoded and executed to

set the Write Enable Latch (WEL) bit in advance. The WRSR

instruction can change the value of Block Protect (BP3, BP2,

BP1, BP0) bits to define the protected area of memory (as

shown in Table 2). The WRSR also can set or reset the Quad

Enhance (QE) bit and set or reset the Status Register Write

Disable (SRWD) bit in accordance with Write Protection (

W )

pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of

the status register. The WRSR instruction cannot be executed

once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: S goes low→

sending WRSR instruction code→ Status Register data on

DI→ S goes high. (Please refer to Figure 19-1 and Figure

19-2)

The S must go high exactly at the byte boundary;

otherwise, the instruction will be rejected and not executed.

The self-timed Write Status Register cycle time (tW) is initiated

as soon as Chip Select ( S ) goes high. The Write in Progress

(WIP) bit still can be check out during the Write Status

The WIP sets 1 during the tW

timing, and sets 0 when Write Status Register Cycle is

completed, and the Write Enable Latch (WEL) bit is reset.

A25LQ64M-FE fixes QE bit “1”, when using this type, the

Hardware Protected Mode (HPM) is disabled.

Table 6. Protection Modes

Mode

Status register condition

W and SRWD bit status

Memory

Software protection

mode (SPM)

Status register can be written in (WEL

bit is set to "1") and the SRWD,

BP0-BP3 bits can be changed

W =1 and SRWD bit=0, or

W =0 and SRWD bit=0, or

W =1 and SRWD=1

The protected area cannot be

program or erase.

Hardware protection

mode (HPM)

The SRWD, BP0-BP3 of status

W =0, SRWD bit=1

The protected area cannot be

program or erase.

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.

2. When using A25LQ64M-FE, the Hardware Protected Mode (HPM) is disabled.

As the above table showing, the summary of the Software

Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

- When SRWD bit=0, no matter

W is low or high, the

WREN instruction may set the WEL bit and can change

the values of SRWD, BP3, BP2, BP1, BP0.

The

protected area, which is defined by BP3, BP2, BP1, BP0,

is at software protected mode (SPM).

- When SRWD bit=1 and

W is high, the WREN instruction

may set the WEL bit can change the values of SRWD, BP3,

BP2, BP1, BP0. The protected area, which is defined by

BP3, BP2, BP1, BP0, is at software protected mode (SPM).

Note:

If SRWD bit=1 but

W is low, it is impossible to write the

Status Register even if the WEL bit has previously been set.

It is rejected to write the Status Register and not be executed.

When using A25LQ64M-FE, the Hardware Protected Mode

(HPM) is disabled.

Hardware Protected Mode (HPM):

- When SRWD bit=1, and then

W is low (or W is low

before SRWD bit=1), it enters the hardware protected mode

(HPM). The data of the protected area is protected by

software protected mode by BP3, BP2, BP1, BP0 and

hardware protected mode by the

W to against data

modification. When using A25LQ64M-FE, the Hardware

Protected Mode (HPM) is disabled.

Note:

To exit the hardware protected mode requires

W driving

high once the hardware protected mode is entered. If the

W pin is permanently connected to high, the hardware

protected mode can never be entered; only can use

software protected mode via BP3, BP2, BP1, BP0.

If the system enter QPI or set QE=1, the feature of HPM will

be disabled.

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