PDSP16488AMA datasheet(13/30 Pages) MITEL

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PDSP16488A MA

FUNCTION

Field selection defined by C5:4

Automatic field selection

DELOP = 29 + 0 clks

DELOP = 29 + 8 clks

DELOP = 29 + 16 clks

DELOP = 29 + 24 clks

DELOP = 29 + 32 clks

DELOP = 29 + 40 clks

DELOP = 29 + 48 clks

DELOP = 29 + 56 clks

Select upper 20 bits

Select next 20 bits

Select bottom 20 bits

By-pass the gain control

Normal gain control O/P

Saturate at max + and -ve values.

Force -ve to zero.Sat.+ve values.

CODE

000

001

010

011

100

101

110

111

BIT

3:1

5:4

7:6

BIT 7

This bit must be set if the pixel clock is greater than

20MHz. It disables the output and input time

multiplexing, and instead outputs the least signifi-

cant half of the 32 bit intermediate sum for the

complete clock cycle. When the gain control is

used, the output multiplexing will automatically be

disabled.

BIT 0

This bit defines the input for the second group of

line delays. It must be set in the 16 bit pixel modes,

and is set by power on reset.

BIT 2:1

These bits control the mode of operation of the line

stores. In real time systems pixels can be stored

either until HRES [ SYNC ] goes active , or until a

pre-determined count is reached. In the frame

store mode line store operations are continuous,

with a pre-determined line length.

BIT 3

When this bit is set four pipeline delays are added

to the pixel inputs to compensate for the internal/

external delays between line stores. The extra

delay is only necessary when a device supplied

with system video in which the first pixel in a line

is valid in the period following the first active clock

edge. See Fig 7. The delay is not necessary if the

device is fed from the output of another convolver.

When set this bit will add four additional delays to

those defined by Register D, bits 4: 2.

BIT 4

When this bit is set the expansion adder will not be

used. It is automatically set in a MASTER or SIN-

GLE device.

BIT 7

This bit controls the bypass option on the first line

delay on the L7:0 inputs. It is only effective when

an 8 bit pixel mode is selected, which also needs

more than four line delays. When L7:0 are used as

outputs it should always be reset. In the 16 bit

modes the bypass function is only controlled by the

BYPASS pin, and the bit is redundant.

FUNCTION

Second line delay group fed from the

first group

Second line delay group fed from L7:0

which become inputs

Store pixels to end of line

Store pixels till count is reached

Frame store operation

Not Used

No delays on pixel inputs

4 delays on both pixel inputs

Use expansion adder

Expansion adder disabled

Not used

Use first delay in second group

Bypass first delay in second group

BIT

2:1

6:5

CODE

BIT 0

If this bit is set, the 20 bit field selected from the 32

bit result, is defined automatically by internal logic.

BITS 3:1 These bits are in conjunction with Register D, bits

7:5 to define the pixel delay from the HRES input

to the DELOP pin. They are used to match the

appropriate processing delay in a particular sys-

tem. The minimum delay is 29 pixel clocks.

BITS 5:4 These bits define which of the four 20 bit fields out

of the 32 bit final result is selected as the input to

the gain control. They are redundant when the gain

control is not used, or if Register C, bit0, is set.

BITS 7:6 These bits define the use of the gain control as

given in the table. Intermediate devices in a mul-

tiple device system MUST by-pass the gain con-

trol, otherwise the additional pipeline delays will

effect the result. Disabling the scaler will reduce

the device pipeline by 13 PCLK cycles from the

delays shown in Table 4.

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