PDSP16488AMA datasheet(19/30 Pages) MITEL

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PDSP16488A MA

the normal way and has its

MASTER and SINGLE pins left

open circuit.

The internal convolver sum, in the device producing

the final result, must be delayed by 4 pixels to match the

inherent delay in the expansion output from the other device.

This is actually achieved by delaying the pixel inputs to the line

stores [ Register D bits 3:2 = 01 ]. No additional delay in the

expansion input is needed, but the pipeline delay used to

produce DELOP must be four clocks greater than that given

in Table 4 for a single device. The DELOP output is redundant

in one of the two devices.

Two devices can also be used to support systems

requiring 16 bit pixels. With this approach the 16 x 8 multipli-

cation is mechanized as two 8 x 8 operations, with the results

added together after the most significant half has been shifted

by 8 places to the most significant end. This shift operation is

controlled by Register D, Bit 1. Both convolvers are pro-

grammed to contain the same coefficients. The convolved

output can theoretically grow to 30 bits, and the appropriate

field must be selected before using the gain control.

Examples of this operating mode are shown in Figure

13. Each device must be configured in the same 8 bit pixel

operating mode, but the device producing the final result must

use the 8 place shift option on its internal sum.

The least significant 8 bits of the pixel are connected to

the MASTER device and the most significant 8 bits are

connected to the device producing the final result.. The

internal sum in this device must be delayed by four pixels to

match the delay in the expansion output from the first device.

This is actually achieved by delaying the pixel inputs to the line

stores( Register D, bits 4:2, = 001 ]. The expansion input

needs no additional delay [ Register D bits 1:0 = 10 ].

The actual pixel precision can be any number of pixels

between 8 and 16, and may be a signed or unsigned number.

Any unused, more significant bits, must respectively be either

sign extended or be tied low.

DELOP must have four additional pipeline delays in order

to match the total processing delay.

This output can be

obtained from either device.

FOUR DEVICE SYSTEMS

Four devices, each in the 8x8 mode, can be used to provide

a 16 x 16 window, with 8 bit pixel resolution and 10 MHz clock

rates. The partial sum from the first device in each row must

be delayed by eight pixel clocks before it is added to the result

from the next device. This provides the eight pixel displace-

ment to match the width of the window. The delay is actually

provided by four additional delays in the expansion input to the

next device, plus the inherent four clock delays in outputing

results from the first device. Register D, Bit 0 controls the

additional delay.

The internal convolver sums, in the two devices in the

second row, must be delayed by 12 clocks before they are

added to the result from the first row. This twelve clock delay

is necessary because of the combination of the eight pixel

horizontal displacement delay , and the four clock delay in

outputing the result from the last device in the top row. It is

actually achieved by delaying the pixel inputs to the line stores.

(Register D, bits 3:2 = 11 ].

The DELOP output must have 20 delays additional to

those in a single device. This compensates for the twelve

delays added to the convolver sums in the second row, plus

an additional eight delays to compensate for the partial width

of the first device in the secind row.

Four devices can also be used to give an 8x8 window,

but with a 30 MHz pixel clock. Each device is configured to

provide a 4x4 partial window, but the maximum pixel rate is

reduced from 40 to 30 MHz because of the response of the line

delay expansion circuitry. Intermediate precision is restricted

to 16 bits, since time multiplexed data outputs cannot be used

above 20 MHz.

This configuration requires no additional delay in the

expansion inputs, and the inputs to the line stores in both

devices in the second row must be delayed by 8 clock cycles

[ Register D bits 3:2 = 10 ]. The DELOP output needs twelve

additional clock delays to match the processing delay.

Figures 14 and 15 show non-interlaced and interlaced

versions of the above 8 x 8 and 4 x 4 arrangements

Figure 16 shows how four devices can also be used to

provide an 8x8 window, with 16 bit pixels and 20MHz clock

rates. The expansion data from a previous device needs no

additional delay since the partial window size in each device

is only 4x4. The internal convolver sums from each device in

the second row must be delayed by 8 Clks and the DELOP

output must have 12 additional delays. If this arrangement is

to be used in a non-interlaced application, the field store must

be replaced by four line delays.

SIX DEVICE SYSTEMS

As shown in figure 17, six devices, each in an 8Wx4D

mode using 8 bit pixels, can provide a 16W x 12D window at

20MHz clock rates. Expansion inputs from previous devices

in a row [but not the first device in each row] need an extra 4

Clks of delay since the partial window is eight pixels wide.

Internal convolver sums need a differential delay of 12 Clk

cycles from row to row [ Register D bits 3:2 = 11 ].

The DELOP output must have 32 additional delays to

match the total processing delay.

EIGHT DEVICE SYSTEMS

Two additional chips will extend the above six device

configuration to a 16 x 16 window. Internal convolver sums

must have differential delays of 12 clock cycles between rows,

as in the six device system. The DELOP output needs 44

additional clock delays.

NINE DEVICE SYSTEMS

Nine devices each in the 8 x 8 mode will provide a 24

x 24 window with 8 bit data and 10 MHz pixel clocks. This is

shown in Figure 18. Expansion data inputs from previous

devices in a row [ but not the first device in each row ] need an

extra 4 Clks of delay. The internal convolver sums need

differential delays of 20 Clk cycles between rows. Sixteen of

the latter delays can be provided internally by setting Register

B, bit3, and also Register D, bits 3:2. The four extra delays

must be provided externally.

The DELOP output needs 56 clock delays in addition

to the 29 required for the 8 x 8 single device configuration.

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