HT48R30A datasheet(6/43 Pages) HOLTEK

6 / 43 page

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

VDD

Conditions

tWDT2

Watchdog Time-out Period

(System Clock)

Without WDT

prescaler

1024

tSYS

tWDT3

Watchdog Time-out Period

(RTC OSC)

Without WDT

prescaler

7.812

tRES

External Reset Low Pulse

Width

¾¾

tSST

System Start-up Timer

Period

Wake-up from HALT

1024

tSYS

tINT

Interrupt Pulse Width

¾¾

Functional Description

HT48R30A-1

Rev. 1.10

July 2, 2001

Execution flow

The system clock for the microcontroller is de-

rived from either a crystal or an RC oscillator.

The system clock is internally divided into four

non-overlapping clocks. One instruction cycle

consists of four system clock cycles.

Instruction fetching and execution are

pipelined in such a way that a fetch takes an in-

struction cycle while decoding and execution

takes the next instruction cycle. However, the

pipelining scheme causes each instruction to ef-

fectively execute in a cycle. If an instruction

changes the program counter, two cycles are re-

quired to complete the instruction.

Program counter - PC

The program counter (PC) controls the se-

quence in which the instructions stored in the

program ROM are executed and its contents

specify a full range of program memory.

After accessing a program memory word to fetch

an instruction code, the contents of the program

counter are incremented by one. The program

counter then points to the memory word contain-

ing the next instruction code.

When executing a jump instruction, conditional

skip execution, loading PCL register, subrou-

tine call or return from subroutine, initial reset,

internal interrupt, external interrupt or return

from interrupt, the PC manipulates the pro-

gram transfer by loading the address corre-

sponding to each instruction.

The conditional skip is activated by instruc-

tions. Once the condition is met, the next in-

struction, fetched during the current

instruction execution, is discarded and a

dummy cycle replaces it to get the proper in-

struction. Otherwise proceed with the next in-

struction.

F e tc h IN S T ( P C )

E x ec ut e I N S T ( P C - 1 )

F e tc h IN S T ( P C + 1 )

E x ec ut e I N S T ( P C )

F e tc h IN S T ( P C + 2 )

E x ec ut e I N S T ( P C + 1 )

PC + 1

PC + 2

S yst e m C l o ck

O S C2 ( RC o nl y )

Execution flow

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