DAC7553_14 datasheet(5/26 Pages) TI1

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TIMING CHARACTERISTICS

(1) (2)

SCLK

SYNC

SDIN

D15

D14

D13

D12

D11

D15

Input Word n

Input Word n+1

Undefined

D15

D14

Input Word n

t10

SDO

CLR

DAC7553

SLAS477 – SEPTEMBER 2005

DD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VDD = 2.7 V to 3.6 V

t1(3)

SCLK cycle time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

SCLK HIGH time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

SCLK LOW time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

SYNC falling edge to SCLK falling edge setup

time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

Data setup time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

4.5

Data hold time

VDD = 3.6 V to 5.5 V

4.5

VDD = 2.7 V to 3.6 V

SCLK falling edge to SYNC rising edge

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

Minimum SYNC HIGH time

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

SCLK falling edge to SDO valid

VDD = 3.6 V to 5.5 V

VDD = 2.7 V to 3.6 V

t10

CLR pulse width low

VDD = 3.6 V to 5.5 V

(1)

All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See Serial Write Operation timing diagram Figure 1.

(3)

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

Figure 1. Serial Write Operation

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