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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DP83936AVF Scheda tecnica(PDF) 81 Page - National Semiconductor (TI) |
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DP83936AVF Scheda tecnica(HTML) 81 Page - National Semiconductor (TI) |
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81 / 104 page  90 AC and DC Specifications (Continued) MEMORY WRITE BMODE e 0 ASYNCHRONOUS MODE TLF12597 – 62 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T9 BSCK to Address ValidHold Time 3 26 3 24 3 22 ns T11 BSCK to ADS Low 26 24 22 ns T11b BSCK to ECS Low 19 17 15 ns T11d BSCK to DS Low 17 15 13 ns T12 BSCK to ADS High 24 22 20 ns T12b BSCK to ECS High 29 27 25 ns T12d BSCK to DS High 17 15 13 ns T15 ADS High Width 45 35 25 ns T18 Write Data Strobe Low Width (Note 2) 40 30 20 ns T32a RDYi Asynchronous Setup to BSCK (Note 3) 5 4 3 ns T33a RDYi Asynchronous Hold from BSCK 5 5 5 ns T36 BSCK to Memory Write Data ValidHold Time 350348 346 ns (Note 4) T37 BSCK to MWR (Write) Valid (Note 1) 24 22 20 ns T39 Write Data Valid to DS Low 34 21 7 ns Note 1 For successive read operations MWR remains high Note 2 DS will only be asserted if the bus cycle has at least one wait state inserted Note 3 This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-T samples RDYi low during the T1 cycle the SONIC-T will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during T2 (wait) (This is assuming that programmable wait states are set to 0) Note 4 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing) http www nationalcom 81 |
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