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Motore di ricerca datesheet componenti elettronici |
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DP83936AVF Scheda tecnica(PDF) 88 Page - National Semiconductor (TI) |
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DP83936AVF Scheda tecnica(HTML) 88 Page - National Semiconductor (TI) |
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88 / 104 page  90 AC and DC Specifications (Continued) BUS REQUEST TIMING BMODE e 0 TLF12597 – 68 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T43 BSCK to HOLD High (Note 2) 18 16 14 ns T44 BSCK to HOLD Low (Note 2) 19 17 15 ns T45 HLDA Asynchronous Setup Time to BSCK (Note 5) 7 6 5 ns T46 HLDA Synchronous Deassert Setup Time 765 ns (Note 1) T51 BSCK to Address ADS MWR DS ECS 37 35 33 ns USRk10l and EXUSRk30lTRI-STATE (Note 4) T52 BSCK to Data TRI-STATE 39 37 30 ns T53 BSCK to USRk10l or EXUSRk30l Valid 34 32 30 ns T55 BSCK to Bus Status Valid 29 27 25 ns T55b Sk20l Hold from BSCK 3 3 3 ns Note 1 A block transfer by the SONIC-T can be pre-empted from the bus by deasserting HLDA provided HLDA is asserted T46 before the rising edge of the last T2 in the current access Note 2 The assertion edge for HOLD is dependent upon the PH bit in the DCR2 The default situation is shown wih a solid line in the timing diagram T43 and T44 apply for both modes Also if HLDA is asserted when the SONIC-T wants to acquire the bus HOLD will not be asserted until HLDA has been deasserted first Note 3 Sk20l will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation Note 4 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive these lines without contention Note 5 The HLDA signal is sampled by the SONIC-T on each rising edge of BSCK The maximum set-up time is ((BSCK periodbT45 min spec)b5 ns) HDLA max set-up time is for information only and is not tested http www nationalcom 88 |
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