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DP83936AVF Scheda tecnica(PDF) 84 Page - National Semiconductor (TI) |
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DP83936AVF Scheda tecnica(HTML) 84 Page - National Semiconductor (TI) |
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84 / 104 page ![]() 90 AC and DC Specifications (Continued) MEMORY READ BMODE e 1 SYNCHRONOUS MODE (one wait-state shown) TLF12597 – 65 Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T9 BSCK to Address Valid 3 26 3 24 3 22 ns T11a BSCK to AS Low 17 15 13 ns T11c BSCK to ECS Low 19 17 15 ns T12a BSCK to AS High 17 15 13 ns T12c BSCK to ECS High 19 17 15 ns T13a BSCK to DS Low (Note 3) 16 14 12 ns T13b BSCK to DS High (Note 3) 16 14 12 ns T14 AS Low Width 44 34 24 ns T15a AS High Width 45 35 25 ns T16 Read Data Strobe High Width 45 35 25 ns T17 Read Data Strobe Low Width 40 30 20 ns T19 Address Hold Time from AS 18 14 10 ns T22 Address Valid to AS 962 ns T23a Read Data Setup Time to BSCK 5 4 3 ns T24a Read Data Hold Time from BSCK 5 5 5 ns T28 BSCK to MRW (Read) Valid (Note 1) 26 24 22 ns T30 DSACK01 Setup to BSCK (Note 2) 5 4 3 ns T31 DSACK01 Hold from BSCK 9 8 7 ns Note 1 For successive read operations MRW remains high Note 2 DSACK01 must be synchronized to the bus clock (BSCK) during synchronous mode Note 3 DS will only be asserted if the bus cycle has at least one wait state inserted http www nationalcom 84 |
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