1.0 Pin Descriptions

DP8459 28-pin PCC package

Pin #

POWER SUPPLY

16

DIGITAL V

4

ANALOG V

13

DIGITAL GROUND.

3

ANALOG GROUND.

TTL LEVEL LOGIC INPUTS

5

READ GATE (RG): Read mode control input, active high (logical-one). Assertion causes the PLL to lock to

the ENCODED READ DATA, employing a zero phase start routine. Deassertion causes the PLL to lock the

REFERENCE CLOCK input, also employing a zero phase start routine. READ GATE timing is allowed to

be fully asynchronous.

6, 7, 8

RANGE SELECT 0, 1, 2 (RS0, RS1, RS2): Control the operating frequency range of the VCO. A 2:1

continuously variable sub-range is available within each of 6 allowed selections, enabling the VCO to

operate at any frequency within a 96:1 range from 500 kHz to 50 MHz.

9

CONTROL REGISTER ENABLE (CRE): A logical Low level allows the CONTROL REGISTER CLOCK to

clock data into the Control Register via the CONTROL REGISTER DATA input; a logical HIGH level

latches the register data and issues the information to the appropriate circuitry.

10

CONTROL REGISTER DATA (CRD): Control Register data input.

11

CONTROL REGISTER CLOCK (CRC): Negative edge triggered Control Register clock input.

12

ENCODED READ DATA (ERD): Incoming TTL-level data derived from the storage media; issued from a

pulse detector circuit. Each positive edge represents a single recorded code bit.

14

REFERENCE CLOCK (RFC): A reference frequency input required for DP8459 operation. The RFC

frequency must be accurate and highly stable (crystal or servo derived) and equivalent to the 2F frequency

for the MFM or [2,7] codes (i.e., equal to, but not derived from the VCO frequency).

18

FREQUENCY LOCK CONTROL (FLC): Selects or de-selects the frequency lock function during a READ

operation. Has no effect with READ GATE deasserted; frequency lock is automatically employed for the full

duration of time READ GATE is deasserted regardless of the level of the FLC input. With READ GATE

high and FLC low (logical-zero) the PLL is forced to lock to the pattern frequency selected via the SYNC

PATTERN SELECT inputs. When high (logical-one) frequency lock action is terminated and the PLL

employs a pulse gate to accommodate random disk data patterns. FLC may be tied to PREAMBLE

DETECTED output pin for self-regulated frequency lock control. FLC timing is allowed to be fully

asynchronous.

20, 19

SYNC PATTERN SELECT 0, 1 (SP0, SP1): Control inputs for selection of the preamble type being

employed. These inputs determine the pattern to which the PLL will frequency-lock during preamble

acquisition (if frequency lock is employed) and for which the PREAMBLE DETECTED circuitry searches.

24

COAST (CST): Control for Coast function. The Coast function may be activated when READ GATE is

either high or low. When the COAST input is low (logical-zero), the phase comparator is disabled and held

in a cleared state, allowing the VCO to coast regardless of ENCODED READ DATA input activity (READ

GATE high) or REFERENCE CLOCK input activity (READ GATE low). No other circuit functions are

disturbed. When high (logical-one), the phase comparator operates normally.

27

HIGH-GAIN DISABLE (HGD): Charge Pump gain switch control. When low (logical-zero), the charge pump

input current is the combined value of the currents at both R

(logical-one), charge pump input current is taken from the R

READ GATE or PREAMBLE DETECTED for self-regulated gain control.

TTL LEVEL LOGIC OUTPUTS

15

SYNCHRONIZED CLOCK (SCK): Issues the VCO signal following READ GATE assertion and completion

of zero phase start sequence; issues REFERENCE CLOCK input signal when READ GATE is deasserted.

Multiplexer switching is achieved without glitches.

17

PREAMBLE DETECTED (PDT): Issues a high level (logical-one) following assertion of READ GATE,

completion of the zero phase start sequence, and the detection of approximately 32 sequential pulses of

1T, 2T or 3T period preamble, or 16 sequential pulses of 4T period preamble, depending on state of SYNC

PATTERN SELECT inputs (T = VCO period). Following preamble detection, the output remains latched

high until de-assertion of READ GATE. The PDT output will be at a logical zero state whenever READ

GATE is inactive.

PrintDate=1996/07/31 PrintTime=11:05:40 ds009322 Rev. No. 1

Proof

4

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