DP8459 datasheet(21/35 Pages) NSC

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The 3 dB bandwidth for requirement #3 is deﬁned by the

equation

−3 dB = ωn [2ζ

2 + 1 +{(2

ζ2 +1)2 +1}0.5]0.5

Requirement #4 has been established in order to maximize the

available window margin via PLL dynamics. Conceptually,

window margin is preserved if the loop phase response to

individually displaced bits (jitter) is not allowed to cause

subsequent windows to be readily shifted from the “average”

position. Any window movement from nominal position can

readily degrade the window margin. It can be seen from

Figure

19 that systems employing low values of damping ratio exhibit

a reduced instantaneous response to phase step and thus

display improved jitter rejection with respect to higher damping

ratio systems. Damping ratio, fortunately, is easily regulated by

loop ﬁlter design. It also follows that a low natural frequency

and its associated “slower” instantaneous phase response will

assist in achieving the goal of jitter rejection. However, the

minimum natural frequency limit for the PLL may actually be

imposed on the system by the

e(t) settling time requirement,

the

∆ω

L requirement, or the ω−3 dB requirement. Whichever of

these produces the highest minimum

value must, by

necessity, dominate in the design. The goal of minimizing the

natural frequency in order to maximize jitter rejection,

therefore, may have to defer to one of these other three

criteria.

Requirement #5 is addressed in three ways: 1) the DP8459

itself engages the frequency discriminating action of the Phase

Comparator whenever the READ GATE is deasserted and the

PLL

locks

the

REFERENCE

CLOCK

signal,

thus

guaranteeing re-lock regardless of the initial frequency step; 2)

tying the HIGH GAIN DISABLE pin to the READ GATE input

places the Charge Pump in the high gain mode whenever the

PLL is locked to the REFERENCE CLOCK, producing an

elevated natural frequency and a more rapid locking action; 3)

N = 2 whenever the READ GATE is deasserted, which, in this

example, effectively increases the loop gain by another factor

of 2 with respect to the gain within the preamble, where N = 4.

Determining PLL Response Characteristics

It is expected that the minimum value of

n will be determined

by the residual phase error requirement of #1 rather than the

lock-in range requirement of #2orthe

−3 dB requirement of

#3. This assumption will be checked at the end of the analysis.

System requirements then are as follows:

e(t) ≤ (2 ns) x (2π rad/ 200 ns) = 0.063 radians,

where t = preamble length 8.8 µs

∆ω

L ≈ ±KBZf(s)|s→

∞ ≥ 0.015x5MHzx2π = 471 Krad/sec

−3 dB = ωn[2ζ

2 +1+{(2

ζ2 +1)2 +1}0.5]0.5

≥ 2x10kHzx2π = 126 Kr/s

Requirement #1 calls for

e(8.8 µs) ≤ 0.063 radians. Damping

ratio

ζ varies as the inverse square root of N (see the equation

for Damping Ratio in Section 3.0) such that

PREAMBLE =

√(N

MAX/NPREAMBLE)x ζMIN = √2 x 0.5 = 0.707. Solving the

appropriate equation for

e(t) for various values of ωn with ζ =

0.707, t = 8.8 µs and an expected frequency step of 0.01 x 5

MHzx2

π = 314 Kr/s:

e (8.8 µs)

200 Kr/s

0.606 rad

19.29 ns

300 Kr/s

0.219 rad

6.97 ns

400 Kr/s

0.056 rad

1.78 ns

500 Kr/s

0.0012 rad

0.038 ns

600 Kr/s

−0.0098 rad

0.312 ns

e (8.8 µs)

700 Kr/s

−0.008 rad

0.026 ns

e (8.8µs)|400 Kr/s = 0.056 radian < 0.063 radian

e = 0.056 radian x 200 ns/2π radian = 1.78 ns < 2ns

Thus 400 Kr/s is chosen as the desired natural frequency

within the preamble to satisfy requirement #1.

If the assumption that

e(t) dominates the minimum natural

frequency requirement is correct, then the

∆ω

L requirement of

#2 and the

−3 dB requirement of #3 should be met by the ωn

obtained above. First, examining requirement #2,

f(s)|s→

∞ = R1 (C2 neglected).

Thus,

∆ω

L = KBR1

Rearranging for R

1 = ∆ωL/KB

The equation for R

1 previously derived shows

1 = 2ζωn/KB

Thus,

∆ω

L/KB = 2ζωn/KB

∆ω

L = 2 ζωn

In this case,

n = 400 Kr/s and ζ = 0.707 (preamble), thus

∆ω

L = 400 Kr/sx2x 0.707 = 566 Kr/s > 471 Kr/s

Thus, requirement #2 is met.

Examining requirement #3, where

−3 dB ≥ 2x10kHzx2π

when N equals its maximum value of 8 (minimum frequency

data pattern;

ζ = 0.5):

n(min) = ωn(preamble) x 1/√(NMAX/NPREAMBLE)

= 400 Kr/s x 1/

√2 = 283 Kr/s

−3 dB = ωn(min) [2ζ

2 +1+{(2

ζ2 +1)2+1}0.5]0.5

=283 Kr/s x 1.817 = 514 Kr/s

514 Kr/s ÷ 2

π = 82 kHz > 2x10kHz

Thus requirements #1 through #3 are met, and #4 defers to

the minimum

n established by #1.

Regarding requirement #5, the DP8459 has been conﬁgured

externally in this example such that when the READ GATE is

deasserted, the loop gain will be increased by a factor of 2 due

to the Charge Pump gain switching (R

NOM = RBOOST; HGD

tied to RG) and by an additional factor of 2 due to the decrease

in N from 4 (preamble) to a ﬁxed internal value of 2. The

resulting factor of 4 effective gain elevation results in an

increase in both the natural frequency,

n, and the damping

ratio,

ζ,by √4 = 2. Thus, when READ GATE is deasserted,

n = 2 x 400 Kr/s = 800 Krad/s

ζ = 2 x 0.707 = 1.414

∆ω

L = 2ζωn = 2 x 1.414 x 800 Krad/s = 2.3 Mr/s

COMPONENT CALCULATIONS

The formulae for the ﬁlter components, derived previously, are

A 2:1 ratio of high-to-low Charge Pump gain was chosen for

the derivation of R

NOM and RBOOST. To achieve the 2:1 gain

ratio, R

NOM

must be equal to R

BOOST

while the parallel

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:06:07 ds009322 Rev. No. 1

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