DP8459 datasheet(23/35 Pages) NSC

23 / 35 page

FIGURE 22. Window Speciﬁcation Diagram

4.1 SYNCHRONIZATION WINDOW GENERATION

The DP8459 employs a pulse gate-delay line scheme in the

generation of the synchronization window.

Figure 6 shows a

simpliﬁed block diagram of the pulse gate and delay line

circuitry coupled with the phase locked loop. All elements

except the delay line are assumed to be delayless for

simplicity of analysis. The pulse gate allows a single VCO

edge to be transmitted to the pump down input of the phase

comparator for each arriving ENCODED READ DATA pulse,

while the delay line allows the ENCODED READ DATA pulse

to open (enable) the pulse gate at a predetermined time (t

prior to the arrival of the ERD pulse at the pump up input of the

phase comparator.

Figures 7, 8 and 9 show waveform

diagrams of the capture of nominal, early and late ERD pulses,

respectively. In normal operation where stable lock has been

achieved,

the

time-integrating

action

the

PLL has

established time alignment between the waveforms at the

phase comparator inputs, i.e., both events occur at t

o,on

average. If t

d is set equal to 0.5 x τVCO, the nominal or average

ERD pulse will open the pulse gate at t

o − 0.5 x τVCO, precisely

the midpoint between VCO edges. ERD pulses are then free to

shift to any position (ideally) between VCO edges, that is, they

have an allowed displacement of ±0.5

VCO from the mean,

while yet opening the pulse gate for the passing of the

appropriate VCO edge to the phase comparator and at the

same time being properly captured by the data synchroniza-

tion latch (ﬂip-ﬂop D,

Figure 6 ). The ±0.5

VCO region is

referred to as the synchronization (capture) window.

Any variation in the value of the time delay t

d causes the time

at which the pulse gate is enabled (t

o–td) to shift away from the

VCO waveform midpoint, and thus produces a corresponding

shift in the position of the synchronization (capture) window.

This action, when done in a controlled fashion, is known as

window strobing and is useful for purposes of window skew

compensation, determination of system window margin, and

recovery routines for non-readable data (see Section 4.3).

TL/F/9322-23

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:06:09 ds009322 Rev. No. 1

Proof

DP8459 Scheda tecnica(PDF) 23 Page - National Semiconductor (TI)

DP8459 Scheda tecnica(HTML) 23 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Scheda tecnica Scarica

Link URL