PC87382 datasheet(28/72 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision1.2

3.7.4

SuperI/O Configuration 6 Register (SIOCF6)

This register provides a fast way to disable one or more modules without having to access the Activate register of each; see

Section 3.3.1 on page 24.

Location: Index 26h

Type:

Varies per bit

3.7.5

SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev).

Location: Index 27h

Type:

Bit

76543210

Name

LOCKFDS

General-Purpose

Scratch

Reserved

SER1DIS

IRDIS

Reserved

Reset

00000000

Bit

Type

Description

R/W1

LOCKFDS (Lock Fast Disable Configuration). When set to 1, this bit locks itself, SER1DIS and IRDIS

bits in this register and GLOBEN bit in SIOCF1 register by disabling writing to all of these bits. Once set,

this bit can only be cleared by Hardware reset.

0: R/W bits are enabled for write (default).

1: All bits are RO.

6-5

R/W

General-Purpose Scratch.

Reserved.

R/W

or RO

SER1DIS (Serial Port 1 Disable).

0: Enabled or Disabled, according to Activation bit (default).

1: Disabled.

R/W

or RO

IRDIS (Infrared Disable).

0: Enabled or Disabled, according to Activation bit (default).

1: Disabled.

1-0

Reserved.

Bit

76543210

Name

Chip ID

Chip Rev

Reset

XXXXX

Bit

Description

7-5

Chip ID.

4-0

Chip Rev. These bits identify the device revision.

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