PC87382 datasheet(29/72 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.2

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3.7.6

Clock Generator Control Register (CLOCKCF)

Location: Index 29h

Type:

Varies per bit

Bit

43210

Name

CKEN

CKOUTSEL CK48SEL

CKVALID

LOCKCCF

Reserved

Reset

00000

Bit

Type

Description

R/W or

CKEN (Clock Enable). This bit enables the internal clock of the PC87382. If the clock source selected

by CK48SEL bit is the Clock Generator, CKEN enables the Clock Generator; otherwise it enables the

path from the CLKIN input pin.

0: Clock disabled (default).

1: Clock enabled.

R/W or

CKOUTSEL (Clock Output Select). Selects the clock source to output on DCLKOUT pin.

0: Select Clock Source from CLKIN pin (default).

1: Select Clock Generator Output. Valid only if CK48SEL field is set.

R/W or

CK48SEL (48 MHz Clock Select). Selects the source of the internal 48 MHz clock.

0: The source of the internal 48 MHz clock is CLKIN pin (default).

Use when CLKIN pin is connected to a 48 MHz clock source.

1: The source of the internal 48 MHz clock is the Clock Generator.

Use when CLKIN pin is connected to a 14.31818 MHz clock source.

4RO

CKVALID (Valid Clock Generator, Clock Status). This bit indicates the status of the on-chip, 48 MHz

Clock Generator and controls the generator output clock signal. The PC87382 modules using this clock

may be enabled (see Section 3.3.1 on page 24) only after this bit is read high (generator clock is valid).

0: Generator output clock frozen (default).

1: Generator output clock active (stable and toggling).

R/W1S LOCKCCF (Lock Clock Conﬁguration). When set to 1, this bit locks the CLOCKCF register by

disabling writing to all its bits (including to the LOCKCCF bit itself). Once set, this bit can only be

cleared by Hardware reset.

0: The R/W bits are enabled for write (default).

1: All the bits are Read-Only.

2-0

Reserved.

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