PC87382 datasheet(18/72 Pages) NSC

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Revision 1.2

3.0

Device Architecture and Conﬁguration

The PC87382 comprises a collection of legacy and proprietary functional blocks. Each functional block is described in a sep-

arate chapter. This chapter describes the PC87382 structure and provides all logical device specific information, including

special implementation of generic blocks, system interface and device configuration.

3.1

OVERVIEW

The PC87382 consists of four logical devices, the host interface, and a central set of configuration registers, all built around

a central internal bus. Figure 3 illustrates the blocks and related logic.

The system interface serves as a bridge between the external LPC interface and the internal bus. It supports 8-bit read and

write transactions for I/O and DMA, as defined in Intel’s LPC Interface Speciﬁcation, Revision 1.1.

The central configuration register set is ACPI compliant and supports a PnP configuration. The configuration registers are

structured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification,

Revision 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA chan-

nels and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-

specific parameters are configurable through the configuration registers and distributed to the functional blocks through spe-

cial control signals.

3.2

CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.

3.2.1

The Index-Data Register Pair

Access to the PC87382 configuration registers is via an Index-Data register pair, using only two system I/O byte locations.

The base address of this register pair is determined during VDD Power-Up reset, according to the state of the hardware strap-

ping option on the BADDR pin. Table 6 shows the selected base addresses as a function of BADDR.

Serial

Port 1

Bus

Interface

LCLK

LRESET

LAD3-0

LFRAME

LDRQ

SERIRQ

CLKIN

SIN1

SOUT1

RTS1

DTR1_BOUT1

CTS1

DSR1

DCD1

RI1

IRRX1,IRRX2

IRTX

IRSL0

GPIO

Ports

BADDR

Control Registers

Conﬁg &

Strap

Conﬁg

CLKRUN

TEST

GPIO20,21,23

DLCLK

DLRESET

DLAD3-0

DLFRAME

DLDRQ

DSERIRQ

DCLKRUN

LPC

Bus

Switch

TRIS

GPIO00-04

Figure 3. PC87382 Detailed Block Diagram

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