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LAN9211 Scheda tecnica(PDF) 133 Page - SMSC Corporation |
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LAN9211 Scheda tecnica(HTML) 133 Page - SMSC Corporation |
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133 / 147 page ![]() High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support Datasheet SMSC LAN9211 133 Revision 2.9 (03-01-12) DATASHEET 6.6 PIO Writes PIO writes are used for all LAN9211 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. Note: The “Data Bus” width is 16 bits. Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. Figure 6.5 PIO Write Cycle Timing Table 6.7 PIO Write Cycle Timing SYMBOL DESCRIPTION MIN TYP MAX UNITS tcycle Write Cycle Time 45 ns tcsl nCS, nWR Assertion Time 32 ns tcsh nCS, nWR Deassertion Time 13 ns tasu Address Setup to nCS, nWR Assertion 0 ns tah Address Hold Time 0 ns tdsu Data Setup to nCS, nWR Deassertion 7 ns tdh Data Hold Time 0 ns Data Bus nCS, nWR A[7:1] |
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