LAN9211 datasheet(79/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

Revision 2.9 (03-01-12)

DATASHEET

5.3.1

ID_REV—Chip ID and Revision

This register contains the ID and Revision fields for this design.

5.3.2

IRQ_CFG—Interrupt Configuration Register

This register configures and indicates the state of the IRQ signal.

Offset:

50h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-16

Chip ID. This read-only field identifies this design

9211h

15-0

Chip Revision

0000h

Offset:

54h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:24

Interrupt Deassertion Interval (INT_DEAS). This field determines the

Interrupt Request Deassertion Interval in multiples of 10 microseconds.

Setting this field to zero causes the device to disable the INT_DEAS

Interval, reset the interval counter, and issue any pending interrupts. If a

new, non-zero value is written to this field, any subsequent interrupts will

obey the new setting.

Note:

This field does not apply to the PME interrupt.

R/W

23-15

Reserved

Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one

to this register clears the de-assertion counter in the IRQ Controller, thus

causing a new de-assertion interval to begin (regardless of whether or

not the IRQ Controller is currently in an active de-assertion interval).

Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit

indicates that interrupts are currently in a deassertion interval, and will

not be delivered to the IRQ pin. When this bit is clear, interrupts are not

currently in a deassertion interval, and will be delivered to the IRQ pin.

Master Interrupt (IRQ_INT). This read-only bit indicates the state of the

internal IRQ line, regardless of the setting of the IRQ_EN bit, or the state

of the interrupt de-assertion function. When this bit is high, one of the

enabled interrupts is currently active.

11-9

Reserved

IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the

IRQ pin. When clear, the IRQ output is disabled and permanently

deasserted. This bit has no effect on any internal interrupt status bits.

R/W

7-5

Reserved

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