LAN9211 datasheet(86/147 Pages) SMSC

86 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

5.3.8

TX_CFG—Transmit Configuration Register

This register controls the transmit functions on the LAN9211 Ethernet Controller.

Offset:

70h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-16

Reserved.

Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX

status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX

status pointers are cleared to zero.

Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX

data FIFO of all pending data. When a ‘1’ is written, the TX data pointers

are cleared to zero.

13-3

Reserved

TX Status Allow Overrun (TXSAO). When this bit is cleared, data

transmission is suspended if the TX Status FIFO becomes full. Setting this

bit high allows the transmitter to continue operation with a full TX Status

FIFO.

Note:

This bit does not affect the operation of the TX Status FIFO Full

interrupt.

R/W

Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is

enabled. Any data in the TX FIFO will be sent. This bit is cleared

automatically when STOP_TX is set and the transmitter is halted.

R/W

Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will

finish the current frame, and will then stop transmitting. When the transmitter

has stopped this bit will clear. All writes to this bit are ignored while this bit

is high.

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