LAN9211 datasheet(96/147 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

5.3.16

GPT_CNT-General Purpose Timer Current Count Register

This register reflects the current value of the GP Timer.

5.3.17

WORD_SWAP—Word Swap Control

This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs

inside the LAN9211. The LAN9211 always sends data from the Transmit Data FIFO to the network so

that the low order word is sent first, and always receives data from the network to the Receive Data

FIFO so that the low order word is received first.

Offset:

90h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31-16

Reserved

15-0

General Purpose Timer Current Count (GPT_CNT). This 16-bit field

reflects the current value of the GP Timer.

FFFFh

Offset:

98h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:0

Word Swap. If this field is set to 00000000h, or anything except

0xFFFFFFFFh, the LAN9211 maps words with address bit A[1]=1 to the high

order words of the CSRs and Data FIFOs, and words with address bit

A[1]=0 to the low order words of the CSRs and Data FIFOs. If this field is

set to 0xFFFFFFFFh, the LAN9211 maps words with address bit A[1]=1 to

the low order words of the CSRs and Data FIFOs, and words with address

bit A[1]=0 to the high order words of the CSRs and Data FIFOs.

Note:

Word swap is used in conjunction with the mixed endian

functionality to determine the final byte ordering. Refer to Section

3.7.3, "Mixed Endian Support" for more information.

R/W

NASR

00000000h

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