HT48R10A datasheet(10/42 Pages) HOLTEK

10 / 42 page

HT48R10A-1

Rev. 1.20

July 2, 2001

Interrupt Control Register (INTC;0BH) con-

tains the interrupt control bits to set the en-

able/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all

the other interrupts will be blocked (by clearing

the EMI bit). This scheme may prevent any fur-

ther interrupt nesting. Other interrupt re-

quests may happen during this interval but

only the interrupt request flag is recorded. If a

certain interrupt requires servicing within the

service routine, the EMI bit and the correspond-

ing bit of INTC may be set to allow interrupt

nesting. If the stack is full, the interrupt request

will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupts have a wake-up ca-

pability. As an interrupt is serviced, a control

transfer occurs by pushing the program counter

onto the stack, followed by a branch to a sub-

routine at specified location in the program

memory. Only the program counter is pushed

onto the stack. If the contents of the register or

status register (STATUS) are altered by the in-

terrupt service program which corrupts the de-

sired control sequence, the contents should be

saved in advance.

External interrupts are triggered by a high to

low transition of INT and the related interrupt

request flag (EIF; bit 4 of INTC) will be set.

When the interrupt is enabled, the stack is not

full and the external interrupt is active, a sub-

routine call to location 04H will occur. The in-

terrupt request flag (EIF) and EMI bits will be

cleared to disable other interrupts.

The internal timer/event counter interrupt is

initialized by setting the timer/event counter

interrupt request flag (TF; bit 5 of INTC),

caused by a timer overflow. When the interrupt

is enabled, the stack is not full and the TF bit is

set, a subroutine call to location 08H will occur.

The related interrupt request flag (TF) will be

reset and the EMI bit cleared to disable further

interrupts.

During the execution of an interrupt subroutine,

other interrupt acknowledgments are held until

the "RETI" instruction is executed or the EMI

bit and the related interrupt control bit are set to

1 (of course, if the stack is not full). To return

from the interrupt subroutine, "RET" or "RETI"

may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Labels

Bits

Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

borrow from the high nibble into the low nibble in subtraction; otherwise AC is

cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the "CLR WDT" instruction. PD

is set by executing the "HALT" instruction.

TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in-

struction. TO is set by a WDT time-out.

Unused bit, read as "0"

Status register

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