LM5122ZPWPR datasheet(22/51 Pages) TI1

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SkipCycle

1.2 V

COMP

1.2V

700k

100k

MODE

Skip Cycle

Comparator

1.2V

Diode

Emulation

20mV

Default

150mV

40mV

Hysteresis

LM5122, LM5122-Q1

SNVS954G – FEBRUARY 2013 – REVISED MAY 2016

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Product Folder Links: LM5122 LM5122-Q1

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Device Functional Modes (continued)

Figure 25. MODE Selection

During startup the LM5122 forces diode emulation, for startup into a pre-biased load, while the SS pin voltage is

less than 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater than

1.2 V. If there are no LO pulses during the soft-start period, a 350-ns one-shot LO pulse is forced at the end of

soft-start to help charge the boot strap capacitor. Due to the internal current sense delay, configuring the LM5122

for diode emulation mode should be carefully evaluated if the inductor current ripple ratio is high and when

operating at very high switching frequency. The transient performance during full load to no load in FPWM mode

should also be verified.

7.4.2 MODE Control (Skip Cycle Mode and Pulse Skipping Mode)

Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of

the converter become a significant percentage of the total power delivered to the load. In order to increase the

light load efficiency the LM5122 provides two types of light load operation in diode emulation mode.

The skip cycle mode integrated into the LM5122 controller reduces switching losses and improves efficiency at

light load condition by reducing the average switching frequency. Skip cycle operation is achieved by the skip

cycle comparator. When a light load condition occurs, the COMP pin voltage naturally decreases, reducing the

peak current delivered by the regulator. During COMP voltage falling, the skip cycle threshold is defined as

VMODE –20 mV and during COMP voltage rising, it is defined as VMODE +20 mV. There is 40mV of internal

hysteresis in the skip cycle comparator.

When the voltage at PWM comparator input falls below VMODE –20 mV, both HO and LO outputs are disabled.

The controller continues to skip switching cycles until the voltage at PWM comparator input increases to VMODE

+20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the

response time of the frequency compensation network. The internal hysteresis of skip cycle comparator helps to

produce a long skip cycle interval followed by a short burst of pulses. An internal 700 k

Ω pullup and 100 kΩ

pulldown resistor sets the MODE pin to 0.15 V as a default. Since the peak current limit threshold is set to 750

mV, the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level will

be lower due to the added slope compensation. By adding an external pullup resistor to SLOPE or VCC pin or

adding an external pulldown resistor to the ground, the skip cycle threshold can be programmed. Because the

skip cycle comparator monitors the PWM comparator input which is proportional to the COMP voltage, skip cycle

operation is not recommended when the bypass operation is required.

Conventional pulse skipping operation can be achieved by connecting the MODE pin to ground. The negative 20-

mV offset at the positive input of skip cycle comparator ensures the skip cycle comparator will not trigger in

normal operation. At light or no load conditions, the LM5122 skips LO pulses if the pulse width required by the

regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as

the error amplifier struggles to find an average pulse width for LO in order to maintain regulation at light or no

load conditions.

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